candidate for extremely low power use. Called subthreshold CML or subthreshold source coupled logic (STSCL), the current consumption of each gate can be reduced down to a few tens of picoamps. See also Low-voltage differential signaling (LVDS) A differential standard used primarily for signals between modules. Positive-referenced emitter-coupled logic, a differential signaling standard for high speed inter-module communications References System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 – 3.125 Gbit/s Parallel Interfaces. OIF, October 2002. TFI-5: TDM Fabric to Framer Interface Implementation Agreement. OIF, September 16, 2003 Introduction to LVDS, PECL, and CML, Maxim, https://pdfserv.maximintegrated.com/en/an/AN291.pdf http://www.ee.iitm.ac.in/~nagendra/videolectures/doku.php?id=ee685:start Interfacing between LVPECL, VML, cml and LVDS Levels, http://focus.ti.com/lit/an/slla120/slla120.pdf For more details on design automation and low power design of CML circuits, see: http://lsm.epfl.ch External links JESD204B - a JEDEC Standard for serial data interfacing - Analog Devices JESD204B Overview (slides) - Texas Instruments Logic families