The MicroBlaze is a soft microprocessor core designed for Xilinx field-programmable gate arrays (FPGA). As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs. MicroBlaze was introduced in 2002. Overview In terms of its instruction set architecture, MicroBlaze is similar to the RISC-based DLX architecture described in a popular computer architecture book by Patterson and Hennessy. With few exceptions, the MicroBlaze can issue a new instruction every cycle, maintaining single-cycle throughput under most circumstances. The MicroBlaze has a versatile interconnect system to support a variety of embedded applications. MicroBlaze's primary I/O bus, the AXI interconnect, is a system-memory mapped transaction bus with master–slave capability. Older versions of the MicroBlaze used the CoreConnect PLB bus. The majority of vendor-supplied and third-party IP interface to AXI directly (or through an AXI interconnect). For access to local-memory (FPGA RAM), MicroBlaze uses a dedicated LMB bus, which provides fast on-chip storage. User-defined coprocessors are supported through dedicated AXI4-Stream connections. The coprocessor(s) interface can accelerate computationally intensive algorithms by offloading parts or the entirety of the computation to a user-designed hardware module. Many aspects of the MicroBlaze can be user configured: cache size, pipeline depth (3-stage, 5-stage, or 8-stage), embedded peripherals, memory management unit, and bus-interfaces can be customized. The area-optimized version of MicroBlaze, which uses a 3-stage pipeline, sacrifices clock frequency for reduced logic area. The performance-optimized version expands the execution pipeline to 5 stages, allowing top speeds of more than 700 MHz (on Virtex UltraScale+ FPGA family). Also, key processor instructions which are rarely used but more expensive to implement in hardware can be selectively added/removed (e.g. multiply, divide, and floating point operations). This customization enables a developer to make the appropriate design trade-offs for a specific set of host hardware and application software requirements. With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel. Otherwise it is limited to operating systems with a simplified protection and virtual memory model, e.g. FreeRTOS or Linux without MMU support. MicroBlaze's overall throughput is substantially less than a comparable hard CPU core (such as the ARM Cortex-A9 in the Zynq). Vivado Xilinx's Vivado Design Suite is the development environment for building current MicroBlaze (or ARM - see Zynq) embedded processor systems in Xilinx FPGAs. Older versions used Xilinx's EDK (Embedded Development Kit) development package. Designers use