1.0, an expanded instruction set that is a superset of MIPS64 release 2. It can be broken down into: LoongEXT, general-purpose extensions, 148 instructions LoongVZ, virtualisation extensions to the "VZ" system introduced in MIPS64 release 5, 5 instructions LoongBT, faster x86 and ARM binary translation, 213 instructions LoongSIMD, formerly LoongMMI (in Loongson 2E/F), for 128-bit SIMD, 1014 instructions MIPS SIMD Architecture (MSA), DSP, and VZ modules from MIPS Release 5 The LoongISA instructions were introduced as part of the GS464E cores. The binary translation instructions have the specific benefit of speeding up Intel x86 CPU emulation at a cost of 5% of the total die area. The new instructions help a QEMU hypervisor translate instructions from x86 to MIPS with only a reported 30% performance penalty. LoongISA 2.0 was introduced for the GS464V R2 core, with the release of the Loongson 3 4000 series. Compared to LoongISA 1.0, the DSP module is removed, and a few sets are added: LoongSX LoongASX LoongEXT3 (updated) LoongAMU Loongson SIMD instructions are semi-classified and are unavailable in publicly available compilers and assemblers, Loongson 2F's LoongMMI being the sole exception. A similar status applies to other LoongISA extensions. LoongArch Loongson moved to their own processor instruction set architecture (ISA) in 2021 with the release of the Loongson 3 5000 series. A Loongson developer described it as "...a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64)". The stated rationale was to make Loongson and China not dependent on foreign technology or authorisation to develop their processor capability, whilst not infringing on any technology patents. The ISA has been referred to as "a fork of MIPS64r6" due to a perceived lack of changes judging from instruction listings. In August 2021, Linux maintainers complained that submitted LoongArch code is "...a blind copy of the MIPS code...", however "only with a different name". The LoongArch ISA manual has been made partially available in August 2021 with the publication of its first volume documenting the basic architecture. According to the LoongArch manual, the ISA uses MIPS's privilege model and IRQ mechanism, with other parts mostly following RISC-V's practice: the delay slot is removed and the instruction encoding is changed. Similar to LoongISA, the instruction-set extensions (SIMD and binary translation) are not yet documented, making this functionality unusable. The Register reported