chip each for the CPU and FPU and discrete elements for the MMU and cache unit, but in later versions the MMU and cache unit were combined into one CAMMU chip. Registers and instruction set The Clipper had 16 integer registers (R15 was used as the stack pointer), 16 floating-point registers (limited to 8 in early implementations), plus a program counter (PC), a processor status word (PSW) containing ALU and FPU status flags and trap enables, and a system status word (SSW) containing external interrupt enable, user/supervisor mode, and address translation control bits. User and supervisor modes had separate banks of integer registers. Interrupt handling consisted of saving the PC, PSW, and SSW on the stack, clearing the PSW, and loading the PC and SSW from a memory trap vector. The Clipper was a load/store architecture, where arithmetic operations could only specify register or immediate operands. The basic instruction "parcel" was 16 bits: 8 bits of opcode, 4 bits of source register, and 4 bits of destination register. Immediate-operand forms allowed 1 or 2 following instruction parcels to specify a 16-bit (sign-extended) or 32-bit immediate operand. The processor was uniformly little-endian, including immediate operands. A special "quick" encoding with a 4-bit unsigned operand was provided for add, subtract, load (move quick to register), and not (move complement of quick to register). Addressing modes for load/store and branch instructions were as follows. All displacements were sign-extended. (Rn), d12(Rn), d32(Rn): Register relative with 0, 12- or 32-bit displacement d16(PC), d32(PC): PC-relative d16, d32: absolute [Rx](Rn), [Rx](PC): Register or PC-relative indexed. The index register was not scaled. In addition to the usual logical and arithmetic operations, the processor supported: 32×32→32-bit multiply, divide, and remainder (signed and unsigned) 64-bit shifts and rotates, operating on even/odd register pairs 32×32→64-bit extended multiplies Integer register push/pop (store with pre-decrement, load with post-increment) Subroutine call (push PC, move address of operand to PC) Return from subroutine (pop PC from stack) Atomic memory load and set msbit Supervisor trap More complex macro instructions allowed: Push/pop multiple integer registers Rn–R14 Push/pop multiple floating-point registers Dn–D7 Push/pop user registers R0–R15 Return from interrupt (pop SSW, PSW and PC) Initialize string (store R0 copies of R2 in memory starting at R1) Move and compare characters (length in R0, source in R1, destination in R2) Most instructions allowed an arbitrary stack pointer register to be specified, but except for the user register save/restore,