of any given bus cycle. Depending on its generation, the Q-bus contains 16, 18, or 22 BDAL (Bus Data/Address Line) lines. 16, 18, or 22 BDAL lines are used for the physical address portion of each bus cycle. Eight or 16 DBAL lines are then re-used for the data portion(s) of each bus cycle. Newer generations of the bus allow block mode transfer where a single bus address can be followed by more than one data cycle (with the transfers taking place at consecutive bus addresses). Because the address portion of each bus cycle can not transfer data, the use of block mode means fewer address cycles and more time for data cycles, allowing increased bus data transfer bandwidth. Bus mastery is awarded based on an I/O card's topological proximity to the bus arbitrator (at the logical front of the bus); closer cards are granted priority over further cards. Interrupts can be delivered to the Interrupt Fielding Processor at any of four interrupt priority levels. Within a given level, the cards closer to the IFP (at the front of the bus) take priority over cards further back on the bus. Interrupts are vectored: a card requesting an interrupt has its interrupt vector read by the IFP. In this way, the interrupts from all I/O cards in the system can be distinguished with no ambiguity. Logic minimization As with the Unibus, the signaling was carefully optimized so that the minimum amount of logic is required across the entire bus system. Asynchronous signaling is used but de-skewing of addresses and data is the responsibility of the current bus master, minimizing the complexity of the bus slave devices. The responsibility for timing-out failed bus cycles also is placed in the master devices. Similarly, the complexities of handling interrupt transactions are concentrated into the single Interrupt-Fielding Processor (the PDP-11 or VAX-11 computer) in the system. Compatibility The design of the Q-bus was very closely related to the design of the Unibus both in spirit and in detailed implementation. Adapters were available from Digital and from third parties that allow Q-bus devices to be connected to Unibus-based computers and vice versa. A number of I/O devices were available in either Unibus or Q-bus flavors; some of these devices have minor differences while many others were essentially identical. Soviet clones In Soviet systems (see 1801 series CPU), the Q-Bus architecture is called МПИ (Магистральный Параллельный Интерфейс,