are treated as lumped signals rather than transmission lines. However, the IEEE version of the related MII standard specifies trace impedance. National recommends running traces with series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under long and matched within on length to minimize skew. Gigabit media-independent interface The gigabit media-independent interface (GMII) is an interface between the medium access control (MAC) device and the physical layer (PHY). The interface operates at speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s. The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards. Transmitter signals There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or 100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses a single clock signal recovered from the incoming data. Receiver signals Management signals The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register. Reduced gigabit media-independent interface The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27. Data is clocked on rising and falling edges for 1000 Mbit/s, and on rising edges only for 10/100 Mbit/s. The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s. The