inversely proportional to clock period, the clock frequency increases as a result. Drawbacks One drawback of using source-synchronous clocking is the creation of a separate clock-domain at the receiving device, namely the clock-domain of the strobe generated by the transmitting device. This strobe clock-domain is often not synchronous to the core clock domain of the receiving device. For proper operation of the received data with other data already present in the device, an additional stage of synchronization logic is required to transfer the received data into the core clock-domain of the receiving device. This stage can often be found alongside source synchronous logic. This usually results in greater system complexity compared to globally clocked systems, but the benefits are generally much greater than this increase in complexity. Implementation Variations In bi-directional data transfer buses, two opposing unidirectional strobes can be sent from each device. Often the strobe is free running in this case. That is, the strobe continues to toggle whether there is data being transferred or not. Another variation is the sharing of the same bus to transfer the strobe. In this case the strobe can only be transferred by the device that is sending the data and may require transmission of pre-ambles and post-ambles to indicate the start and end of the strobes. (Example: DDR2). In large ASICs or processors, multiple strobes and data groups (data bits that are associated to the same strobe) may exist between the same two devices to account for the slightly different PVT variations in different regions of the same die. See also Clock recovery 8B/10B encoding Synchronization (computer science) External links Overview of Memory Types and DDR Interface Design Implementation Clock signal Electrical circuits