makes it clear that the source of randomness is thermal, not quantum.) The "Nehemiah+" (C5P) (stepping 8) revision brought a few more advancements, including a high-performance AES encryption engine along with a notably small ball grid array chip package the size of a US 1 cent coin. At the time VIA also boosted the FSB to 200 MHz and introduced new chipsets such as the CN400 to support it. The new 200 MHz FSB chips are only available in BGA packages, as they are not compatible with existing Socket 370 motherboards. When this architecture was marketed it was often referred to as the "VIA C5". Technical information Comparative die size Design methodology While slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock-for-clock basis, VIA's chips were much smaller, cheaper to manufacture, and lower power. This made them highly attractive in the embedded marketplace. This also enabled VIA to continue to scale the frequencies of their chips with each manufacturing process die shrink, while competitive products from Intel (such as the P4 Prescott) encountered severe thermal management issues, although the later Intel Core generation of chips were substantially cooler. C3 Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space. Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios. The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors. Infrequently used x86 instructions are implemented in microcode and emulated. This saves die space and reduces power consumption. The impact upon the majority of real-world application scenarios is minimized. These design guidelines are derivative from the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. As it makes heavy use of memory operands, both as source and destination, the C3