SDRAM memory channels Embedded PCI Express I/O interfaces Security co-processor on each core. Supports DES, 3DES, AES, RC4, SHA-1, SHA-256/384/512, Kasumi, Galois Field, MD5, RSA with up to 2048 key, ECC, CRC. Hardware random number generator 2 embedded 1GigE/10GigE interfaces 2.4 Tbit/s aggregate throughput per socket Systems With the release of the SPARC T3 chip, the new brand of Oracle SPARC T-series servers was introduced to the market, effectively replacing CMT (UltraSPARC T2/T2 Plus) machines from the previous SPARC Enterprise product line. Fewer physical products from the former server line were refreshed with the T3 chip, reducing the total number of servers respectively to four: One Socket SPARC T3-1 2U Rack Server One Socket SPARC T3-1B Blade Server Two Socket SPARC T3-2 Server Four Socket SPARC T3-4 Server Virtualization Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Oracle VM Server for SPARC domains (a feature formerly known as Logical Domains). Performance improvement versus T2 and T2+ The SPARC T3 processor is effectively two T2+ processors on a single die. The T3 has: Double the cores (16) of a T2 or T2+ Double the 10Gig Ethernet ports (2) over a T2+ Double the crypto accelerator cores (16) over a T2 or T2+ Crypto engines support more algorithms than the T2 or T2+ including: DES, Triple DES, AES, RC4, SHA-1, SHA256/384/512, Kasumi, Galois Field, MD5, RSA to 2048 key, ECC, CRC32 Over 1.9x Cryptography Performance Throughput Increase Faster DDR3 RAM interface over the T2 or T2+ DDR2 interface Double the throughput Double the memory capacity Quadruple the I/O throughput Two PCIe 2.0 eight lane interfaces vs one PCIe former generation eight lane interface See also UltraSPARC T1 – The predecessor to T2, also Sun's first chip-multithreaded CPU SPARC T4 References Oracle microprocessors Ultrasparc T3 SPARC microprocessors 64-bit microprocessors