pack (PQFP). It used a 3.3 V power supply, dissipating 1.8 W typically and a maximum of 2 W at 80 MHz. In comparison to the Pentium, SPECint ratings had the Pentium at 64.5 and the R4200 at 55. SPECfp ratings had the Pentium at 56 versus the R4200 at 30. R4300i The R4300i is a derivative of the R4200 designed by MTI for embedded applications announced on 17 April 1995. It differs from the R4200 by featuring an improved integer multiplier with a lower latency and a cut-down 32-bit system bus for reduced cost. The chip had an area of 45 mm2 and was fabricated in a 350 nm process. By employing multiplexed address and data lines, it could be packaged in a low-cost 120-pin PQFP. It uses a 3.3 V power supply and dissipates 1.5 W running at 40 MHz (80 MHz internally), 1.8 W at 100 MHz and 2.2 W at 133 MHz. The R4300i was licensed to NEC and Toshiba, and was marketed by those companies as the VR4300 or TX4300, respectively. Both companies offered 100 and 133 MHz versions. A derivative of the VR4300 was developed by NEC for the Nintendo 64 game console, clocked at 93.75 MHz and labeled NUS-CPU. Although development boards for the Nintendo 64 used stock NEC VR4300 CPUs, the final CPU has been found to be not pin-compatible. This singular use of a MIPS implementation produced significant royalties for MTI, sales for NEC, and made MIPS the highest volume mixed 32/64-bit RISC ISA in 1997. NEC produced two other derivatives of the R4300 for the general embedded market, the VR4305 and VR4310, announced on 20 January 1998. The VR4310 was available at 100, 133 or 167 MHz. It was manufactured in a 250 nm process and packaged in a 120-pin PQFP. References "MIPS, NEC will launch 64-bit device". (17 April 1995). Electronic News. "NEC Unveils New MIPS Chip for Nintendo". (8 May 1995). Microprocessor Report. Gwennap, Linley (31 May 1993). "MIPS Reaches New Lows With R4200 Design". Microprocessor Report, pp. 6–9. Levy, Marcus (15 September 1994). "EDN's 21st Annual Microprocessor Directory". EDN. Ryan, Bob; Thompson, Tom (January 1994). "RISC Grows Up". Byte. Yeung, N.K. et al. (1994). "The design of a 55SPECint92 RISC processor under 2W". ISSCC Digest of Technical Papers. pp. 206–207. Zivkov, B.; Ferguson, B.; Gupta, M. (1994). Compcon Spring '94, Digest of Papers. pp. 18–25. MIPS implementations