cache operated at half or one-third the internal clock frequency: 85 or 56.67 MHz respectively at 170 MHz. It was direct-mapped, had a 32-byte line size and used a write-through write policy. It was parity protected. The cache was built from 12 ns pipelined burst static random access memory (PBSRAM). Memory controller supported 8 to 256 MB of fast page mode (FPM) DRAM in eight banks. The L2 cache and memory were accessed using the system bus, a 72-bit wide bus, of which 64 bits were for data. The AFX interface enabled AFX graphics cards to directly access the memory. It shares the same data bus with the cache and memory controllers but used its own control lines. The SBus controller had its own 16-entry input/output translation lookaside buffer. TurboSPARC supported SBus frequencies of 16.67 to 25 MHz. The TurboSPARC was not multiprocessor-capable. The TurboSPARC contained 3.0 million transistors and measured 11.5 by 11.5 mm for a die area of 132.25 mm2. It was fabricated by Fujitsu in their CS-60ALE process, a 0.35 µm four-level metal complementary metal–oxide–semiconductor (CMOS) process. The TurboSPARC was packaged in a 416-ball plastic ball grid array (PBGA). It used a 3.3 V power supply and had a 9 W maximum power dissipation. Notes References Fujitsu Microelectronics, Inc. (30 September 1996). Fujitsu Microelectronics' New TurboSPARC Processor Sets New Performance Level For Low-End, Mid-Range Workstations. Press release. Gwennap, Linley (18 November 1996). "TurboSPARC Offers Low-End Upgrade". Microprocessor Report, pp. 14–16. Fujitsu microprocessors SPARC microprocessors 32-bit microprocessors