same as the destination, a conditional move (CMOV). Integer vector shift and rotate instructions The shift instructions here differ from those in SSE2 in that they can shift each unit with a different amount using a vector register interpreted as packed signed integers. The sign indicates the direction of shift or rotate, with positive values causing left shift and negative right shift Intel has specified a different incompatible set of variable vector shift instructions in AVX2. Vector permute VPPERM is a single instruction that combines the SSSE3 instruction PALIGNR and PSHUFB and adds more to both. Some compare it the Altivec instruction VPERM. It takes three registers as input, the first two are source registers and the third the selector register. Each byte in the selector selects one of the bytes in one of the two input registers for the output. The selector can also apply effects on the selected bytes such as setting it to 0, reverse the bit order, and repeating the most-significant bit. All of the effects or the input can in addition be inverted. The VPERMIL2PD and VPERMIL2PS instructions are two source versions of the VPERMILPD and VPERMILPS instructions in AVX which means like VPPERM they can select output from any of the fields in the two inputs. Floating-point fraction extraction These instructions extracts the fractional part of floating point, that is the part that would be lost in conversion to integer. CPUs with XOP AMD: "Heavy Equipment" processors Bulldozer-based processors, Q4 2011 Piledriver-based processors, Q4 2012 Steamroller-based processors, Q1 2014 Excavator-based processors (including "v2"), 2015 See also AVX CVT16 FMA4 SSE5 x86 Notes References X86 instructions SIMD computing AMD technologies