The maximum random access memory (RAM) installed in any computer system is limited by hardware, software and economic factors. The hardware may have a limited number of address bus bits, limited by the processor package or design of the system. Some of the address space may be shared between RAM, peripherals, and read-only memory. In the case of a microcontroller with no external RAM, the size of the RAM array is limited by the size of the integrated circuit die. In a packaged system, only enough RAM may be provided for the system's required functions, with no provision for addition of memory after manufacture. Software limitations to usable physical RAM may be present. An operating system may only be designed to allocate a certain amount of memory, with upper address bits reserved to indicate designations such as I/O or supervisor mode or other security information. Or the operating system may rely on internal data structures with fixed limits for addressable memory. For mass-market personal computers, there may be no financial advantage to a manufacturer in providing more memory sockets, address lines, or other hardware than necessary to run mass-market software. When memory devices were relatively expensive compared with the processor, often the RAM delivered with the system was much less than the address capacity of the hardware, because of cost. Sometimes RAM limits can be overcome using special techniques. Bank switching allows blocks of RAM memory to be switched into the processor's address space when required, under program control. Operating systems routinely manage running programs using virtual memory, where individual program operate as if they have access to a large memory space that is being simulated by swapping memory areas with disk storage. CPU addressing limits For performance reasons, all the parallel address lines of an address bus must be valid at the same time, otherwise access to memory would be delayed and performance would be seriously reduced. Integrated circuit packages may have a limit on the number of pins available to provide the memory bus. Different versions of a CPU architecture, in different-sized IC packages, can be designed, trading off reduced package size for reduced pin count and address space. A trade-off might be made between address pins and other functions, restricting the memory physically available to an architecture even if it inherently has a higher capacity. On the other hand, segmented or bank switching designs provide more memory