also the performance. Depending on the manufacturing technology of integrated passives high capacitance or resistor values with a required tolerance may be hard to meet. Q value of coils/inductors might also be limited by the thickness of the metals available in the implementation. However new materials and improved manufacturing techniques like atomic layer deposition (ALD) and understanding manufacturing and control of thick metal alloys on large substrates improve capacitance density and Q value of coils/inductors. Therefore in prototyping and small/medium size production phase standard parts/passives are in many cases the fastest way to the realization. Custom designed passives can be considered to be used after careful technical and economical analysis in volume manufacturing, if time-to-market and cost targets of the product(s) can be met. Therefore integrated passive devices are continuously technically and economically challenged by decreasing size, improving tolerances, improving accuracy of assembly techniques (like SMT, surface-mount technology) of system motherboards and cost of discrete/separate passive devices. Going forward discrete and integrated passives will complement each other technically. Development and understanding of new materials and assembly techniques are a key enabler for both integrated and discrete passive devices. Fabrication IPDs on a silicon substrate IPDs on a silicon substrate are generally fabricated using standard wafer fabrication technologies such as thin film and photolithography processing. For avoiding possible parasitic effects due to semiconductive silicon high resistive silicon substrate is typically used for integrated passives. IPDs on silicon can be designed as flip chip mountable or wire bondable components. However to differentiate technically from active integrated circuit (IC) technologies IPD technologies may utilise thicker metal (for higher Q value of inductors) or different resistive (like SiCr) layers, thinner or different higher K (higher dielectric constant) dielectric layers (like PZT instead of silicon dioxide or silicon nitride) for higher capacitance density than with typical IC technologies. IPDs on silicon can be grinded — if needed — below 100 µm in thickness and with many packaging options (micro-bumping, wire bonding, copper pads) and delivery mode options (as wafers, bare dies, tape & reel). 3D passive integration in silicon is one of the technologies used to manufacture Integrated Passive Devices (IPDs), enabling high-density trench capacitors, metal-insulator-metal (MIM) capacitors, resistors, high-Q inductors, PIN, Schottky or Zener diodes to be implemented in silicon. The design time of IPDs on silicon depends on complexity of the design but can be made by using same design tools and environment