of contact elements. MEMS type is the most advanced technology currently available. The most advanced type of probe card currently can test an entire 12" wafer with one touchdown. Probe cards or DUT boards are designed to meet both the mechanical and electrical requirements of the particular chip and the specific test equipment to be used. One type of DUT board is used for testing the individual die of a silicon wafer before they are cut free and packaged, and another type is used for testing packaged IC's. Efficiency factors Probe card efficiency is affected by many factors. Perhaps the most important factor impacting probe card efficiency is the number of DUTs that can be tested in parallel. Many wafers today are still tested one device at a time. If one wafer had 1000 of these devices and the time required to test one device was 10 seconds and the time for the prober to move from one device to another device was 1 second, then to test an entire wafer would take 1000 x 11 seconds = 11,000 seconds or roughly 3 hours. If however, the probe card and the tester could test 16 devices in parallel (with 16 times the electrical connections) then the test time would be reduced by almost exactly 16 times (to about 11 minutes). Contamination issues Another major factor is debris that accumulates on the tips of the probe needles. Normally these are made of tungsten or tungsten/rhenium alloys or advanced palladium based alloys like PdCuAg. Some modern probe cards have contact tips manufactured by MEMS technologies. Irrespective of the probe tip material, contamination builds up on the tips as a result of successive touchdown events (where the probe tips make physical contact with the bond pads of the die). Accumulation of debris has an adverse effect on the critical measurement of contact resistance. To return a used probe card to a contact resistance that is acceptable, the probe tips must be spotless. Cleaning can be done offline using an NWR style laser to reclaim the tips by selectively removing the contamination. Online cleaning can be used during testing to optimize the testing results within the wafer or within wafer lots. Notes References External links Additional Slides for Lecture 16: "Testing, Design for Testability", EE271 System-in-Package (SiP) Testing, Jin-Fu Li, National Central University, Taiwan Probe Card Tutorial, Keithley Instruments Semiconductor device fabrication Hardware testing