& control signals. The serialized stream is sent along with a reference clock. The clock jitter tolerance at the serializer is 5–10 ps rms. Embedded Clocking An embedded clock SerDes serializes data and clock into a single stream. One cycle of clock signal is transmitted first, followed by the data bit stream; this creates a periodic rising edge at the start of the data bit stream. As the clock is explicitly embedded and can be recovered from the bit stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80–120 ps rms, while the reference clock disparity at the deserializer can be ±50,000 ppm (i.e. 5%). Data Encoding 8b/10b SerDes maps each data byte to a 10-bit code before serializing the data. The deserializer uses the reference clock to monitor the recovered clock from the bit stream. As the clock information is synthesized into the data bit stream, rather than explicitly embedding it, the serializer (transmitter) clock jitter tolerance is to 5–10 ps rms and the reference clock disparity at the deserializer is ±100 ppm. A common coding scheme used with SerDes is 8b/10b encoding. This supports DC-balance, provides framing, and guarantees frequent transitions. The guaranteed transitions allow a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The typical 8b/10b SerDes parallel side interfaces have one clock line, one control line and 8 data lines. Such serializer-plus-8b/10b encoder, and deserializer-plus-decoder blocks are defined in the Gigabit Ethernet specification. Another common coding scheme used with SerDes is 64b/66b encoding. This scheme statistically delivers DC-balance and transitions through the use of a scrambler. Framing is delivered through the deterministic transitions of the added framing bits. Such serializer-plus-64b/66b encoder and deserializer-plus-decoder blocks are defined in the 10 Gigabit Ethernet specification. The transmit side comprises a 64b/66b encoder, a scrambler, and a gearbox that converts the 66b signal to a 16-bit interface. Another serializer then converts this 16-bit interface into a fully serial signal. Bit interleaved SerDes Bit interleaved SerDes multiplexes several slower serial data streams into faster serial streams, and the receiver demultiplexes the faster bit streams back to slower streams. Standardization of SerDes The Optical Internetworking Forum (OIF) has published the Common Electrical I/O (CEI) Interoperability Agreements (IAs), that have defined six generations of the electrical interface of SerDes, at 3.125, 6, 10, 28, 56 and 112 Gb/s. The OIF has announced