represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase. During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance). Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously when it is valid. Also, when both A and B are high, so that the output is low, the circuit will pump one capacitor load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the A and B inputs are constant and both high, the dynamic NAND gate uses power in proportion to the clock rate, as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low. This, in turn, reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit derived from an equilibrium between clock speed and load capacitance. A popular implementation is domino logic. See also Domino logic Sequential logic References General references Chapter 9, "Dynamic logic circuits" (chapter 7 in the 2nd edition) Chapter 14, "Dynamic logic gates" Chapter 7, "Dynamic SOI Design" External links Introduction to CMOS VLSI Design – Lecture 9: Circuit Families – David Harris' lecture notes on the subject. Logic families