a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal. In particular, although many popular CPUs use dynamic logic, only static cores—CPUs designed with fully static technology—are usable in space satellites owing to their higher radiation hardness. When properly designed, dynamic logic can be over twice as fast as static logic. It uses only the faster N transistors, which improves transistor sizing optimizations. Static logic is slower because it has twice the capacitive loading, higher thresholds, and uses slow P transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days require dynamic logic, although some manufacturers such as Intel have designed chips using completely static logic to reduce power consumption. Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost. In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS. There are several powersaving techniques that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic. Static logic example As an example, consider the static logic implementation of a CMOS NAND gate: This circuit implements the logic function If A and B are both high, the output will be pulled low. If either A or B are low, the output will be pulled high. At all times, the output is pulled either low or high. Dynamic logic example Consider now a dynamic logic implementation of the same logic function: The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase, and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which