circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic. In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, stray capacitance causes it to maintain a level within some tolerance range of the driven level. Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven. Static logic has no minimum clock rate—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to three advantages: being able to pause a system at any time makes debugging and testing much easier, enabling techniques such as single stepping. being able to run a system at extremely low clock rates allows low-power electronics to run longer on a given battery. a fully-static system can instantly resume exactly where it left off; a person doesn't have to wait for the system to boot up or resume. Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins (for example, RDY on the 6502), or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. The hardware logic must gate the latch control inputs as necessary to ensure that