circuit schematic. If the two netlists match, then the circuit passes the LVS check. At this point it is said to be "LVS clean." (Mathematically, the layout and schematic netlists are compared by performing a Graph isomorphism check to see if they are equivalent.) In most cases the layout will not pass LVS the first time requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include: Shorts: Two or more wires that should not be connected have been and must be separated. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device) Missing Components: An expected component has been left out of the layout. Parameter Mismatch: Components in the netlist can contain properties. The LVS tool can be configured to compare these properties to a desired tolerance. If this tolerance is not met, then the LVS run is deemed to have a Property Error. A parameter that is checked may not be an exact match, but may still pass if the lvs tool tolerance allows it. (example: if a resistor in a schematic had resistance=1000 (ohms) and the extracted netlist had the a matched resistor with resistance=997(ohms) and the tolerance was set to 2%, then this device parameter would pass as 997 is within 2% of 1000 ( 997 is 99.7% of 1000 which is within the 98% to 102% range of the acceptable +-2% tolerance error) ) Software Commercial software Assura, Dracula and PVS by Cadence Design Systems Calibre by Mentor Graphics Guardian LVS by Silvaco Quartz LVS by Magma Design Automation IC Validator by Synopsys PowerLVS -now SmartLVS by Silvaco SmartLVS by Silvaco VERI and HVERI by Zeni EDA Free software KLayout https://klayout.de/ Netgen http://opencircuitdesign.com/netgen/ References Electronic circuit verification