prefetch as opposed to 16 bytes in K8 DRAM prefetcher for buffering reads Buffered burst writeback to RAM in order to reduce contention Changes in memory hierarchy: Prefetch directly into L1 cache as opposed to L2 cache with K8 family 32-way set associative L3 victim cache sized at least 2 MB, shared between processing cores on a single die (each with 512 K of independent exclusive L2 cache), with a sharing-aware replacement policy. Extensible L3 cache design, with 6 MB planned for 45 nm process node, with the chips codenamed Shanghai. Changes in address space management: Two 64-bit independent memory controllers, each with its own physical address space; this provides an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environments. This approach is in contrast to the previous "interleaved" design, where the two 64-bit data channels were bounded to a single common address space. Larger Tagged Lookaside Buffers; support for 1 GB page entries and a new 128-entry 2 MB page TLB 48-bit memory addressing to allow for 256 TB memory subsystems Memory mirroring (alternatively mapped DIMM addressing), data poisoning support and Enhanced RAS AMD-V Nested Paging for improved MMU virtualization, claimed to have decreasing world switch time by 25%. Improvements in system interconnect: HyperTransport retry support Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket. Platform-level enhancements with additional functionality: Five p-states allowing for automatic clock rate modulation Increased clock gating Official support for coprocessors via HTX slots and vacant CPU sockets through HyperTransport: Torrenza initiative. Feature tables CPUs CPU features table APUs APU features table Desktop Phenom models Agena (65 nm SOI, quad-core) Four AMD K10 cores L1 cache: 64 KB instruction and 64 KB data (data + instructions) per core L2 cache: 512 KB per core, full-speed L3 cache: 2 MB shared between all cores Memory controller: dual channel DDR2-1066 MHz with unganging option ISA extensions: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, AMD64, Cool'n'Quiet, NX bit, AMD-V Socket AM2+, HyperTransport with 1600 to 2000 MHz Power consumption (TDP): 65, 95, 125 and 140 Watt First release November 19, 2007 (B2 Stepping) March 27, 2008 (B3 Stepping) Clock rate: 1800 to 2600 MHz Models: Phenom X4 9100e - 9950 Toliman (65 nm SOI, tri-core) Three AMD K10 cores L1 cache: 64 KB instruction and 64 KB data cache per core L2