an AM3 K10 processor supports both DDR2 and DDR3. A few AM3 motherboards have both DDR2 and DDR3 slots (this does not mean that both types can be fitted at the same time), but for the most part they have only DDR3. Lynx desktop processors only support DDR3, as they use the FM1 socket. Microarchitecture characteristics Characteristics of the microarchitecture include the following: Form factors Socket AM2+ with DDR2 for the 65 nm Phenom and Athlon 7000 Series Socket AM3 with either DDR2 or DDR3 for Semprons and the 45 nm Phenom II and Athlon II Series. They can also be used on AM3+ motherboards with DDR3. Note that, while all K10 Phenom Processors are backwards compatible with Socket AM2+ and Socket AM2, some 45 nm Phenom II Processors are only available for Socket AM2+. Lynx processors do not use either AM2+ nor AM3. Socket FM1 with DDR3 for Lynx processors. Socket F with DDR2, DDR3 with Shanghai and later Opteron processors Instruction set additions and extensions New bit-manipulation instructions ABM: Leading Zero Count (LZCNT) and Population Count (POPCNT) New SSE instructions named as SSE4a: combined mask-shift instructions (EXTRQ/INSERTQ) and scalar streaming store instructions (MOVNTSD/MOVNTSS). These instructions are not found in Intel's SSE4 Support for unaligned SSE load-operation instructions (which formerly required 16-byte alignment) Execution pipeline enhancements 128-bit wide SSE units Wider L1 data cache interface allowing for two 128-bit loads per cycle (as opposed to two 64-bit loads per cycle with K8) Lower integer divide latency 512-entry indirect branch predictor and a larger return stack (size doubled from K8) and branch target buffer Side-Band Stack Optimizer, dedicated to perform increment/decrement of register stack pointer Fastpathed CALL and RET-Imm instructions (formerly microcoded) as well as MOVs from SIMD registers to general purpose registers Integration of new technologies onto CPU die: Four processor cores (Quad-core) Split power planes for CPU core and memory controller/northbridge for more effective power management, first dubbed Dynamic Independent Core Engagement or D. I. C. E. by AMD and now known as Enhanced PowerNow! (also dubbed Independent Dynamic Core Technology), allowing the cores and northbridge (integrated memory controller) to scale power consumption up or down independently. Shutting down portions of the circuits in core when not in load, named "CoolCore" Technology. Improvements in the memory subsystem: Improvements in access latency: Support for re-ordering loads ahead of other loads and stores More aggressive instruction prefetching, 32 bytes instruction