patterning is not prohibitive, but more like a nuisance and growing expense. 5nm may be expected in 2020, with the evolution of multiple patterning and status of EUV considered at that time. 7nm and 5nm FinFETs Self-aligned quadruple patterning (SAQP) is already the established process to be used for patterning fins for 7 nm and 5 nm FinFETs. With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma). Among the four logic/foundry manufacturers, only Intel is applying SAQP to the metal layers, as of 2017. DRAM Like NAND Flash, DRAM has also made regular use of multiple patterning. Even though the active areas form a two-dimensional array, one cut mask is sufficient for 20 nm. Furthermore, the cut mask may be simultaneously used for patterning the periphery, and thus would not count as an extra mask. When the active area long pitch is ~3.5 x the short pitch, the breaks in the active area form a hexagonal array, which is amenable to the triangular lattice spacer patterning mentioned above. Samsung has already started manufacturing the 18 nm DRAM. NAND flash Planar NAND flash had several layers which use SADP below 80 nm pitch and SAQP below 40 nm pitch. 3D NAND flash used SADP for some layers. While it does not scale so aggressively laterally, the use of string stacking in 3D NAND would imply the use of multiple patterning (litho-etch style) to pattern the vertical channels. Typically, for NAND, SADP patterns a set of lines from a core mask, followed by using a trim mask to remove the loop ends, and connecting pads with a third mask. EUV Multipatterning EUV multiple patterning is not ruled out, especially for 5nm node. This is due to a number of reasons. First, there is the tightening tip-to-tip (T2T) spec, representing the minimum distance between metal line ends. In addition, the distance between cuts must not be too small as to expose portions of lines in between. When minimum pitch is reduced to 32 nm or less, stochastic defects are prevalent enough to reconsider double patterning at larger design widths. At pitches of ~30 nm or less, the illumination is also restricted to extremely low pupil fills below 20%, which causes a significant portion of the EUV source power to be unused. This lowers the throughput considerably. Hence, multiple patterning for EUV at wider design