tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness. The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other. Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking. The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned. When SADP is repeated, an additional halving of the pitch is achieved. This is often referred to as self-aligned quadruple patterning (SAQP). With 76 nm being the expected minimum pitch for a single immersion lithography exposure, 19 nm pitch is now accessible with SAQP. Self-aligned contact/via patterning Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells and is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias. Since 32 nm node, Intel has applied the above-mentioned self-aligned via approach, which allows two vias separated by a small enough pitch (112.5 nm for Intel 32 nm metal) to be patterned with one resist opening instead of two separate ones. If the vias were separated by less than the single exposure pitch resolution limit, the minimum required number of masks would be reduced, as two separate masks for the originally separated via pair can now be replaced by a single mask for the same pair. Spacer-is-dielectric (SID) SADP In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer