the EUV mask features and the illumination shape simultaneously have indicated that different patterns in the same metal layer could require different illuminations. On the other hand, a single exposure only offers a single illumination. For example, in a cross-pitch source-mask optimization for 7nm node, for 40-48 nm pitch and 32 nm pitch, the quality as determined by the normalized image log slope was insufficient (NILS<2), while only 36 nm pitch was barely satisfactory for bidirectional single exposure. The underlying situation is that EUV patterns may be split according to different illuminations for different pitches, or different pattern types (e.g., staggered arrays vs. regular arrays). This could apply to line-cutting patterns as well as contact/via layers. It is also likely more than one cut would be needed, even for EUV. At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node. A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size. However, some products, such as NVIDIA's Pascal Tesla P100, will be bisected by the half-field size, and therefore require stitching of two separate exposures. In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan. Multipatterning implementations Memory patterns are already patterned by quadruple patterning for NAND and crossed quadruple/double patterning for DRAM. These patterning techniques are self-aligned and do not require custom cutting or trim masks. For 2x-nm DRAM and flash, double patterning techniques should be sufficient. Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive. As of 2016, Intel was using SADP for its 10 nm node; however, as of 2017, the 36 nm minimum metal pitch is now being achieved by SAQP. Intel is using triple patterning for some critical layers at its 14 nm node, which is the LELELE approach. Triple patterning is already demonstrated in 10 nm tapeout, and is already an integral part of Samsung's 10 nm process. TSMC is deploying 7 nm in 2017 with multiple patterning; specifically, pitch-splitting, down to 40 nm pitch. Beyond the 5 nm node, multiple patterning, even with