ICALL, and all load and store addressing modes except indirect via Z. A second, more successful attempt to subset the AVR instruction set is the "AVR tiny" core. The most significant change is that the AVRtiny core omits registers R0–R15. The registers are also not memory-mapped, with I/O ports from 0–63 and general-purpose RAM beginning at address 64. The 16-bit arithmetic operations (ADIW, SBIW) are omitted, as are the load/store with displacement addressing modes (Y+d, Z+d), but the predecrement and postincrement addressing modes are retained. The LPM instruction is omitted; instead program ROM is mapped to the data address space and may be accessed with normal load instructions. Finally, the AVRtiny core deletes the 2-word LDS and STS instructions for direct RAM addressing, and instead uses the opcode space previously assigned to the load/store with displacement instructions for new 1-word LDS and STS instructions which can access the first 128 locations of general-purpose RAM, addresses 0x40 to 0xBF. (The IN and OUT instructions provide direct access to I/O space from 0 to 0x3F.) Memory addressing instructions The smallest cores have ≤256 bytes of data address space (meaning ≤128 bytes of RAM after I/O ports and other reserved addresses are removed) and ≤8192 bytes (8 KiB) of program ROM. These have only an 8-bit stack pointer (in SPL), and only support the 12-bit relative jump/call instructions RJMP/RCALL. (Because the AVR program counter counts 16-bit words, not bytes, a 12-bit offset is sufficient to address 213 bytes of ROM.) Additional memory addressing capabilities are present as required to access available resources: Models with >256 bytes of data address space (≥256 bytes of RAM) have a 16-bit stack pointer, with the high half in the SPH register. Models with >8 KiB of ROM add the 2-word (22-bit) JUMP and CALL instructions. (Some early models suffer an erratum if a skip instruction is followed by a 2-word instruction.) Models with >64 KiB of ROM add the ELPM instruction and corresponding RAMPZ register. LPM instructions zero-extend the ROM address in Z; ELPM instructions prepend the RAMPZ register for high bits. This is not the same thing as the more general LPM instruction; there exist "classic" models with only the zero-operand form of ELPM (ATmega103 and at43usb320). When auto-increment is available (most models), it updates the entire 24-bit address including RAMPZ. (Rare) models with >128 KiB of ROM have a 3-byte program counter. Subroutine calls and