only operate on a subset of those registers. I/O registers have a dedicated 6-bit address space, the lower half of which is bit-addressable; some parts have I/O registers outside this address space, which are called "extended I/O" and are only accessible as memory-mapped I/O in the data address space. The data address space maps the 32 general-purpose registers, all the I/O registers (including those also accessible through the I/O address space), and the RAM; it can be addressed either directly or indirectly through the X, Y and Z pointer registers, prepended if necessary by RAMPX, RAMPY and RAMPZ respectively. Program memory (flash) has a separate address space, addressed as 16-bit words for the purpose of fetching instructions For the purpose of fetching constant data, program memory is addressed bytewise through the Z pointer register, prepended if necessary by RAMPZ. The EEPROM is memory-mapped in some devices; in others, it is not directly addressable and is instead accessed through address, data and control I/O registers. The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant. The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as " ()" through " ()", where the first item is the I/O address and the second, in parentheses, the data address. The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 KiB of addressable memory. A typical ATmega memory map may look like: where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at . Instruction timing Arithmetic operations work on registers R0–R31 but not directly on RAM and take one clock cycle, except for multiplication and word-wide addition (ADIW and SBIW) which take two cycles. RAM and I/O space can be accessed only by copying to or from registers. Indirect access (including optional postincrement, predecrement or constant displacement) is possible through registers X, Y, and Z. All accesses to RAM takes two clock cycles. Moving between registers and I/O is one cycle. Moving eight or sixteen bit data between registers or constant to register is also one cycle. Reading program memory (LPM) takes three cycles. Instruction list