returns use an additional byte of stack space, there is a new EIND register to provide additional high bits for indirect jumps and calls, and there are new extended instructions EIJMP and EICALL which use EIND:Z as the destination address. (The previous IJMP and ICALL instructions use zero-extended Z.) (Rare) models with >64 KiB of RAM address space extend the 16-bit RAM addressing limits with RAMPX, RAMPY, RAMPZ and RAMPD registers. These provide additional high bits for addressing modes which use the X, Y, or Z register pairs, respectively, or the direct addressing instructions LDS/STS. Unlike ROM access, there are no distinct "extended" instructions; instead the RAMP registers are used unconditionally. Optional feature instructions Three instructions are present only on models which have the corresponding hardware facility SPM for storing to flash ROM, is present only on processors with flash ROM (most of them) BREAK for invoking the on-chip debugger, is omitted on some small models without on-chip debugger support DES for performing Data Encryption Standard rounds, is present on XMEGA models with DES accelerator support Architectures other than AVR1 are named according to avr-libc conventions. Reduced register set is limited to R16 through R31. Instruction encoding Bit assignments: = Source register = Source register (R16–R31) = Source register (R16–R23) RRRR = Source register pair (R1:R0–R31:R30) = Destination register = Destination register (R16–R31) = Destination register (R16–R23) DDDD = Destination register pair (R1:R0–R31:R30) pp = Register pair, W, X, Y or Z y = Y/Z register pair bit (0=Z, 1=Y) u = FMUL(S(U)) signed with 0=signed or 1=unsigned s = Store/load bit (0=load, 1=store) c = Call/jump (0=jump, 1=call) cy = With carry (0=without carry, 1=with carry) e = Extend indirect jump/call address with EIND (0=0:Z, 1=EIND:Z) q = Extend program memory address with RAMPZ (0=0:Z, 1=RAMPZ:Z) = I/O space address = I/O space address (first 32 only) = Bit number (0–7) B = Bit value (0 or 1) = 4-bit unsigned constant (DES opcode) = 6-bit unsigned constant = 8-bit constant The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/store with offset instructions are the most extreme example where a 6-bit offset is broken into three pieces. References External links GNU Development Environment: Programming the AVR microcontroller with GCC by Guido Socher A GNU Development Environment for the AVR Microcontroller by Rich Neswold AVR Options in GCC-AVR AVR Instruction Set