2.0 use 128b/132b encoding, which is identical to 64b/66b, but duplicates each of the preamble bits to reduce the risk of undetected errors there. Successors For each {n}b/{n+2}b encoding, the symbol/data ratio is always below 1. With a ratio of 0.985 for 128b/130b encoding, there is no real margin for improvement. The following approaches are available to further increase the data rate: Higher symbol rates combined with FEC Very common are 512b/514b encodings combined with Reed–Solomon error correction. The following variants are often used: RS(528,514,7,10), adding 14 correction bits to the 512b/514b code word, allowing to correct up to 7 corrupted bits. Overhead is 3%, same as 64b/66b encoding RS(544,514,14,10), adding 30 correction bits to the 512b/514b code word, allowing to correct up to 15 corrupted bits. Overhead is 6%. The FEC allows symbol error rates of 2.3 · 10−5 or 2.2 · 10−4 to achieve a bit error rate of less than 10−15 in the transmitted data. Multi-level encoding combined with FEC Further improvements are possible by switching from PAM-2 to PAM-4 or Ensemble NRZ coding. Multi-level Trellis modulation combined with FEC Technologies that use 64b/66b encoding 100 Gigabit Ethernet 10G-EPON, 10 Gbit/s Ethernet Passive Optical Network 10 Gigabit Ethernet (most varieties) Aurora, from Xilinx Camera Link HS Common Public Radio Interface Fibre Channel 10GFC and 16GFC InfiniBand Thunderbolt JESD204C Technologies that use 128b/1xxb encoding NVLink 1.0 PCIe 3.x PCIe 4.x PCIe 5.x SATA 3.2 SAS 4 USB 3.1 Gen2 USB4 DisplayPort 2.0 Technologies that use 256b/257b encoding Fibre Channel 32GFC "Gen 6" and higher References External links 64b/66b low-overhead coding proposal for serial links (update 1/12/00) Note that this is the original proposal to the IEEE, and some changes were made for the final, agreed standard. The circuit diagram for the 58-bit scrambling polynomial described in the proposal is identical to the one adopted in the standard. However, the proposal numbers the registers in reverse order such that the x58+x19+1 polynomial in the proposal is the same as the one labelled x58+x39+1 in the standard. US Patent/US6650638: Decoding method and decoder for 64b/66b coded packetized serial data US Patent/US6718491: Coding method and coder for packetized serial data with low overhead US Patent/US7055073: Coding method for coding packetized serial data with low overhead PatentView/EP1133123 Software Patent: 64b/66b decoding, for packetized serial data ERROR CORRECTION ON 64/66 BIT ENCODED LINKS Introduction to 10 Gigabit 64b/66b (Clause 49) A reference design