The chips produced there are apparently only for IBMs own Cell blade servers, which were the first to get the 65 nm Cells. Sony introduced the third generation of the PS3 in November 2007, the 40GB model without PS2-compatibility which was confirmed to use the 65 nm Cell. Thanks to the shrunk Cell, power consumption was reduced from 200W to 135W. At first it was only known that the 65 nm-Cells clock up to 6 GHz and run on 1.3V core voltage, as demonstrated on the ISSCC 2007. This would have given the chip a theoretical peak performance of 384GFLOPS in FP8 quarter precision (48GFLOPs in FP64 dual precision), a significant improvement to the 204.8GFLOPS peak (25.6GFLOPs FP64 dual precision) that a 90 nm 3.2 GHz Cell could provide with 8 active SPUs. IBM further announced it implemented new power-saving features and a dual power supply for the SRAM array. This version was not yet the long-rumoured "Cell+" with enhanced Double Precision floating point performance, which first saw the light of day mid-2008 in the Roadrunner supercomputer in the form of QS22 PowerXCell blades. Although IBM talked about and even showed higher-clocked Cells before, clock speed has remained constant at 3.2 GHz, even for the double precision enabled "Cell+" of the Roadrunner. By keeping clockspeed constant, IBM has instead opted to reduce power consumption. PowerXCell clusters even best IBMs Blue Gene clusters (371MFLOPS/watt), which are far more power-efficient already than clusters made up of conventional CPUs (265MFLOPS/watt and lower). Future editions in CMOS Prospects at 45 nm At ISSCC 2008, IBM announced Cell at the 45 nm node. IBM said it would require 40 percent less power at the same clockspeed than its 65 nm predecessor and that the die area would shrink by 34 percent. The 45 nm Cell requires less cooling and allows for cheaper production, also through the use of a much smaller heatsink. Mass production was initially slotted to begin in late 2008 but was moved to early 2009. Prospects beyond 45 nm Sony, IBM and Toshiba announced to begin work on a Cell as small as 32 nm in January 2006, but since process shrinks in fabs usually happen on a global and not an individual chip scale, this was merely as a public commitment to take Cell to 32 nm. References Cell BE architecture