The Parallax P8X32A Propeller is a multi-core processor parallel computer architecture microcontroller chip with eight 32-bit reduced instruction set computer (RISC) central processing unit (CPU) cores. Introduced in 2006, it is designed and sold by Parallax, Inc. The Propeller microcontroller, Propeller assembly language, and Spin interpreter were designed by Parallax's cofounder and president, Chip Gracey. The Spin programming language and Propeller Tool integrated development environment (IDE) were designed by Chip Gracey and Parallax's software engineer Jeff Martin. On August 6, 2014, Parallax Inc. released all of the Propeller 1 P8X32A hardware and tools as open-source hardware and software under the GNU General Public License (GPL) 3.0. This included the Verilog code, top-level hardware description language (HDL) files, Spin interpreter, PropellerIDE and SimpleIDE programming tools and compilers. Multi-core architecture Each of the eight 32-bit cores (termed a cog) has a central processing unit (CPU) which has access to 512 32-bit long words (2 KB) of instructions and data. Self-modifying code is possible and is used internally, for example, as the boot loader overwrites itself with the Spin Interpreter. Subroutines in Spin (object-based high-level code) use a call-return mechanism requiring use of a call stack. Assembly (PASM, low-level) code needs no call stack. Access to shared memory (32 KB random-access memory (RAM); 32 KB read-only memory (ROM)) is controlled via round-robin scheduling by an internal computer bus controller termed the hub. Each cog also has access to two dedicated hardware counters and a special video generator for use in generating timing signals for PAL, NTSC, VGA, servomechanism-control, and others. Speed and power management The Propeller can be clocked using either an internal, on-chip oscillator (providing a lower total part count, but sacrificing some accuracy and thermal stability) or an external crystal oscillator or ceramic resonator (providing higher maximum speed with greater accuracy at higher total cost). Only the external oscillator may be run through an on-chip phase-locked loop (PLL) clock multiplier, which may be set at 1x, 2x, 4x, 8x, or 16x. Both the on-board oscillator frequency (if used) and the PLL multiplier value may be changed at run-time. If used correctly, this can improve power efficiency; for example, the PLL multiplier can be decreased before a long no operation wait needed for timing purposes, then increased afterward, causing the processor to use less power. However, the utility of this technique is limited to situations where no other cog is executing timing-dependent