2 KB in size), will be copied into the dedicated RAM of a cog and will then start interpreting bytecode in the main 32 KB RAM. Additional cogs can be started from that point, loading a separate copy of the interpreter into the new cog's dedicated RAM (a total of eight interpreter threads can, thus, run simultaneously). Notably, this means that at least a minimal amount of startup code must be Spin code, for all Propeller applications. Syntax Spin's syntax can be divided into blocks, which hold: VAR – global variables CON – program constants PUB – code for a public subroutine PRI – code for a private subroutine OBJ – code for objects DAT – predefined data, memory reservations and assembly code Example keywords reboot: causes the microcontroller to reboot waitcnt: wait for the system counter to equal or exceed a specified value waitvid: waits for a (video) timing event before outputting (video) data to I/O pins coginit: starts a processor on a new task Example program An example program, (as it would appear in the Propeller Tool editor) which emits the current system counter every 3,000,000 cycles, then is shut down by another cog after 40,000,000 cycles: The Parallax Propeller is gradually accumulating software libraries which give it similar abilities to Parallax's older BASIC Stamp product; however there is no uniform list of which PBASIC facilities now have Spin equivalents. It has been jokingly opined that "If two languages were to meet in a bar – Fortran and BASIC – nine months later one would find Spin." This refers to the whitespace formatting of FORTRAN and the keyword-based operation of BASIC. Package and I/O The initial version of the chip (called the P8X32A) provides one 32-bit port in a 40-pin 0.6 in dual in-line package (DIP), 44-pin LQFP, or Quad Flat No-leads package (QFN) surface-mount technology package. Of the 40 available pins, 32 are used for I/O, four for power and ground pins, two for an external crystal (if used), one to enable power outage and brownout detection, and one for reset. All eight cores can access the 32-bit port (designated "A"; there is currently no "B") simultaneously. A special control mechanism is used to avoid I/O conflicts if one core attempts to use an I/O pin as an output while another tries to use it as input. Any of these pins can be used for the timing