called stack machines: All arithmetic operations take place using the top one or two positions on the stack: push a, push b, add, pop c. C = A+B needs four instructions. For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory. 1-operand (one-address machines), so called accumulator machines, include early computers and many small microcontrollers: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit accumulator as the left operand (and the destination if there is one): load a, add b, store c. C = A+B needs three instructions. 2-operand — many CISC and RISC machines fall under this category: CISC — move A to C; then add B to C. C = A+B needs two instructions. This effectively 'stores' the result without an explicit store instruction. CISC — Often machines are limited to one memory operand per instruction: load a,reg1; add b,reg1; store reg1,c; This requires a load/store pair for any memory movement regardless of whether the add result is an augmentation stored to a different place, as in C = A+B, or the same memory location: A = A+B. C = A+B needs three instructions. RISC — Requiring explicit memory loads, the instructions would be: load a,reg1; load b,reg2; add reg1,reg2; store reg2,c. C = A+B needs four instructions. 3-operand, allowing better reuse of data: CISC — It becomes either a single instruction: add a,b,c C = A+B needs one instruction. CISC — Or, on machines limited to two memory operands per instruction, move a,reg1; add reg1,b,c; C = A+B needs two instructions. RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed: load a,reg1; load b,reg2; add reg1+reg2->reg3; store reg3,c; C = A+B needs four instructions. Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse. more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the VAX "POLY" polynomial evaluation instruction. Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, TI MSP430, and some versions of ARM Thumb. RISC architectures that