clock cycles transfer a nibble containing the DMA channel number, and a second nibble giving the transfer size. The memory address is programmed into the ISA-style DMA controller in the chipset or the CPU outside of the LPC bus. See the section on DMA below. ISA-compatible reads and writes Memory and I/O accesses are allowed as single-byte accesses only. For a write, the address described above is followed by the data field, 8 bits transferred with the least significant nibble first over two cycles. Following this, the host turns the bus over to the device. This turn-around takes two cycles, and operates the same way as the conventional PCI bus control signals: for one cycle, the host drives the LAD lines high (1111). During the second cycle, the host ceases to drive the lines, although they remain high due to the pull-up resistors. The device may drive the lines beginning with the third cycle. Following any turn-around to the device is a minimum of one SYNC cycle. The number is variable, under the control of the device to add as many wait states as it needs. The bit patterns 0101 and 0110 indicate that the sync cycles will continue. The wait ends when the device drives a pattern of 0000 (ready) or 1010 (error) on the LAD bus for one cycle. In the case of reads, this is followed by 8 bits of data, transferred least significant nibble first over two cycles, the same as for a write. The device then turns the bus around to the host again (taking another two cycles), and the transfer is complete; the host may send the START field of another transfer on the next cycle. If the host attempts a transfer to an unused address, no device will drive the SYNC cycles and the host will see 1111 on the LAD bus. After seeing three cycles of 1111 (two cycles are allowed, in addition to the two turn-around cycles, for a slow device to decode the address and begin driving SYNC patterns), the host will abort the operation. ISA-compatible DMA The Platform Controller Hub (PCH) chip or the southbridge chip acts as the host and controls the LPC bus. It also acts as the central DMA controller for devices on that bus if the memory controller is in the chipset. In CPUs that contain their own memory controller(s), the DMA controller is located