on the host (south bridge). LRESET#: Active-low bus reset. May be connected to PCIRST#. LFRAME#: This active-low signal indicates the beginning of an LPC bus transaction. Driven by the host only. LAD[3:0]: These four bidirectional signals carry multiplexed address, data, and other information. Like the previous two control signals, these signals have weak pull-up resistors on them, so they will remain in the all-ones state if not actively driven by a device. There are six additional signals defined, which are optional for LPC devices that do not require their functionality, but support for the first two is mandatory for the host: LDRQ#: DMA/bus master request. This is an output from a device that wants to perform direct memory access, either via the Intel 8237 compatible DMA controller, or the LPC-specific bus master protocol. The host must provide one corresponding input pin per device that needs it (minimum two). SERIRQ: Serialized Intel 8259 compatible interrupt signal. One line is shared by all LPC devices and the host. CLKRUN#: Open-collector signal used to restart the clock in systems that can stop it for power management. Not required if the host does not stop the clock. May be connected to the equivalent PCI signal. LPME#: Open-collector power management event, to wake the system from a sleep state. Equivalent to the PCI bus PME# signal. LPCPD#: Optional output from the host to warn the LPC device that power is about to be removed and it should not make any interrupt or DMA requests. LSMI#: System management interrupt request. This is only required if an LPC device needs to trigger an SMI# in response to a bus access (e.g. to perform software emulation of a missing hardware peripheral). Otherwise, the slower SERIRQ protocol can be used to request an SMI. Timing and performance The LPC bus derives its electrical conventions from those of conventional PCI. In particular, it shares the restriction that two idle cycles are required to "turn around" any bus signal so that a different device is "speaking". In the first, the bus is actively driven high. In the second, the bus is undriven and held high by the pull-up resistors. A new device may begin sending data over the bus on the third cycle. LPC operations spend a large fraction of their time performing such turn-arounds. As mentioned, the LPC bus is designed to have performance similar to the ISA bus. The