when performing a memory transfer, does not use an ISA-style DMA channel, and can support 8, 16, or 32-bit transfers; while 16-bit ISA bus mastering requires a 24-bit memory address when performing a memory transfer, requires the use of an ISA-style DMA channel, and cannot perform 32-bit transfers. START = 1111 Transaction abort At any time, although typically in response to an error by the device during a SYNC field, the host may abort the current transaction by driving LFRAME# low without waiting for the current transaction to end. It must hold it low for at least 4 cycles, then return it high with a special START field value of 1111. This performs a soft reset of the LPC bus and leaves the bus idle until the next transfer is commenced by driving LFRAME# low again. START = 0101 TPM Locality access Recent Trusted Platform Module specifications define special TPM-Read cycles and TPM-Write cycles that are based on the I/O Read and the I/O Write cycles. These cycles use a START field with the formerly-reserved value of 0101 and place a 16-bit memory address offset in the address field. These cycles are used when using a TPM's locality facility. Supported peripherals The LPC bus specification limits what type of peripherals may be connected to it. It only allows devices that belong to the following classes of devices: super I/O devices, nonvolatile BIOS memory, firmware hubs, and embedded controllers. Furthermore, each class is restricted on which bus cycles are allowed for each class. Super I/O devices and audio devices are allowed to accept I/O cycles, accept ISA-style third-party DMA cycles, and generate bus master cycles. Generic-application memory devices like nonvolatile BIOS memory and LPC flash devices are allowed to accept memory cycles. Firmware hubs are allowed to accept firmware memory cycles. Embedded controllers are allowed to accept I/O cycles and generate bus master cycles. Some ISA cycles that were deemed not useful to these classes were removed. They include host-initiated two-byte memory cycles and host-initiated two-byte I/O cycles. These removed transfer types could be initiated by the host on ISA buses but not on LPC buses. The host would have to simulate two-byte cycles by splitting them up into two one-byte cycles. The ISA bus has a similar concept because the original 8-bit ISA bus required 16-bit cycles to be split up. Therefore, the 16-bit ISA bus automatically split 16-bit cycles