write, where data is transferred from the device, the SYNC field is followed by the 8 bits of data and another SYNC field, until the host-specified length for this transfer is reached, or the device stops the transfer. A two-cycle turnaround field completes the transaction. For a DMA read, where data is transferred to the device, the SYNC field is followed by a turnaround, and the data—turnaround—sync—turnaround sequence repeats for each byte transferred. Serialized interrupts Serialized interrupts are transmitted over a single shared SERIRQ line with the help of the clock. A time slot is dedicated to each interrupt request, with the initial synchronization being done by the host. As a simplified example: The host drives the SERIRQ line low for eight clocks, then high for another, and lets the bus float for a final turnaround cycle. If a device needs to request IRQ#6, it waits for 6×3=18 clocks, then drives SERIRQ low for a clock and high for another. The devices can synchronize at the first step because the line can only be driven low for two or more consecutive clocks by the host: no other device drives it low for more than one clock. The host recognizes the sources of the interrupts by watching the line while counting the number of clocks: if it sees the SERIRQ line being driven low at the eighteenth clock, then IRQ 18/3=6 is asserted. The above is the continuous mode, where the host initiates the protocol. In the quiet mode, a device requests interruption by driving SERIRQ low for a clock. The host then continues driving the line low for the other seven clocks. From this point on, the protocol is the same. In both modes, the number of clocks of the initial synchronization pulse may range from four to eight. At the beginning, the protocol works in continuous mode. At the end of each complete bus transaction (after the host has driven SERIRQ low and then waited for all devices to send interrupt requests) the host sends a final message: it drives the SERIRQ line low for two or three clocks depending on the mode that will be used in the next transaction. The advantage of using serialized interrupts over the traditional mechanism is that only the single SERIRQ line is necessary (apart from the clock, which is present anyway), not a line for each interrupt level. LPC non-ISA cycles START