exact data transfer rates depend on the type of bus access (I/O, memory, DMA, firmware) performed and by the speed of the host and the LPC device. All bus cycles except the 128-byte firmware read cycle, in which 256 of the 273 clock ticks consumed by this cycle actually are used to transfer data to get a throughput of 15.63 MB/s, spend a majority of their time in overhead rather than data transfer. The next fastest bus cycle, the 32-bit ISA-style DMA write cycle that is defined in this standard, can transfer up to 6.67 MB/s because only 8 out of 20 clock ticks used in this bus cycle actually transfer data while the rest of the cycles are overhead. One of the slowest bus cycles is a simple memory read or write, where only 2 of the 17 clock ticks (plus any wait states imposed by the device) transfer data, for a transfer rate of 1.96 MB/s. Applications Intel designed the LPC bus so that the system BIOS image could be stored in a single flash memory chip directly connected to the LPC bus. Intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the LPC bus, as an alternative to a Parallel ATA port. A CPLD or FPGA can implement an LPC host or peripheral. The original Xbox game console has an LPC debug port that can be used to force the Xbox to boot new code. ISA-compatible operation All LPC bus transactions are initiated by the host briefly driving LFRAME# low, for one cycle at least. During the last cycle with LFRAME# low (referred to as the START field), the host drives LAD[3:0] to all-zeros to indicate an ISA-compatible transaction will follow. During the first cycle with LFRAME# high again, the host drives a "cycle type/direction" (CTDIR) field: three bits indicating the type (I/O, memory, or DMA) and direction (read from device, or write to device) of the transfer to follow. This is usually followed by the transfer address field. The size of the address depends on the type of cycle: For I/O access, the address is 16 bits, transferred most-significant nibble first over 4 cycles. For system memory access, the address is 32 bits, transferred most-significant nibble first over 8 cycles. ISA-style DMA accesses do not have an address per se, but a two