The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures. The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage devices and supercomputers. Applied Micro Circuits Corporation (AMCC) bought assets concerning the 400 family cores from IBM in April 2004 for $227 million, and they now market the processors under their own name. IBM continues evolving the cores while supplying design and foundry services around the cores. Several cores are also available for licensing by OEMs from IBM and Synopsys. Variants PowerPC 403 Introduced in 1994, the PowerPC 403 was one of the first PowerPC processors. It was the first one targeted strictly to the embedded market. Compared to the other PowerPC processors of the era (PowerPC 601, PowerPC 603 and PowerPC 604), it was at the very low end, lacking a memory management unit (MMU) or floating point unit (FPU), for instance. The core was offered for custom chips and in pre packaged versions, including versions with MMU, speeds ranging from 20 to 80 MHz. The PowerPC 403 is used in, among other appliances, thin clients, set-top boxes, RAID-controllers, network switches and printers. The first TiVo used a 54 MHz PowerPC 403GCX. AMCC acquired the design of 403 from IBM in 2004, but have chosen not to market it, instead focusing on the 405 and 440 cores. PowerPC 401 While the 403 was popular, it was also too high performance and too costly for some applications, so in 1996 IBM released a bare bones PowerPC core, called PowerPC 401. It has a single issue, three-stage pipeline, with no MMU or DMA and only 2 KB instruction and 1 KB data L1 caches. The design contained just 85,000 transistors in all and operated at up to 100 MHz, drawing only 0.1 W or less. Applications using the 401 core range from set-top boxes and telecom switches to printers and fax machines. PowerPC 405 The PowerPC 405 was released in 1998 and was designed for price or performance sensitive low-end embedded system-on-a-chip (SoC) designs. It has a five-stage pipeline, separate 16 KB instruction and data L1 caches, a CoreConnect bus, an Auxiliary Processing Unit (APU) interface for expandability and supports clock rates exceeding 400 MHz. The 405 core adheres