to the Power ISA v.2.03 using the Book III-E specification. Both AMCC and IBM are developing and marketing processors using 405 cores. IBM and Synopsys also offers a fully synthesizable core. IBM has announced plans to make the specifications of the PowerPC 405 core freely available to the academic and research community. PowerPC-405-based applications include digital cameras, modems, set-top boxes (IBM's STB04xxx processors), cellphones, GPS-devices, printers, fax machines, network cards, network switches, storage devices and service processors for servers. Up to two 405 cores are used in Xilinx Virtex-II Pro and Virtex-4 FPGAs. In 2004 Hifn bought IBM's PowerNP network processors that uses 405 cores. Later versions of the PlayStation 2 slim used a PowerPC 405 chip emulating the MIPS R3000A that was used as the I/O processor in earlier models. The Chinese company Culturecom uses a 405 core for its V-Dragon processor which powers Linux terminals and set-top-boxes. The V-Dragon processor includes the Multilingual Character Generation Engine (MCGE) that processes and generates Chinese characters directly in the CPU. APM801xx AppliedMicro has a series of system on a chip products based on PowerPC 405 core, under a new name: APM801xx. These are the most energy efficient Power Architecture products to date (Fall 2010), and supports frequencies up to 800 MHz at ~1 W, or 0.3 W idling. Made to support a wide range of applications from networking, to storage and media devices. POWER8 on-chip controller The POWER8 processor contains an embedded on-chip power and thermal management microcontroller, called on-chip controller (OCC). Based on a PowerPC 405 processor with 512 KB of dedicated static RAM (SRAM), OCC monitors the entire chip. PowerPC 440 Introduced in 1999, the PowerPC 440 was the first PowerPC core from IBM to include the Book E extension to the PowerPC specification. It also included the CoreConnect bus technology designed to be the interface between the parts inside a PowerPC based system-on-a-chip (SoC) device. It is a high-performance core with separate 32 KB instruction and data L1 caches, a seven-stage out-of-order dual-issue pipeline, supporting speeds of up to 800 MHz and L2 caches up to 256 KB. The core lacks a floating point unit (FPU) but it has an associated four-stage FPU that can be included using the APU (Auxiliary Processing Unit) interface. The 440 core adheres to the Power ISA v.2.03 using the Book III-E specification. Xilinx currently incorporates one or two cores (depending on the