aggressive on the last; his designs tended to use components that were already in widespread use, as opposed to leading-edge designs. For the Cray-2, he introduced a novel 3D-packaging system for its integrated circuits to allow higher densities, and it appeared that there was some room for improvement in this process. For the new design, he stated that all wires would be limited to a maximum length of . This would demand the processor be able to fit into a block, about that of the Cray-2 CPU. This would not only increase performance but make the system 27 times smaller. For a 12x performance increase, the packaging alone would not be enough, the circuits on the chips themselves would also have to speed up. The Cray-2 appeared to be pushing the limits of the speed of silicon-based transistors at 4.1 ns (244 MHz), and it did not appear that anything more than another 2x would be possible. If the goal of 12x was to be met, more radical changes would be needed, and a "high tech" approach would have to be used. Cray had intended to use gallium arsenide circuitry in the Cray-2, which would not only offer much higher switching speeds but also used less energy and thus ran cooler as well. At the time the Cray-2 was being designed, the state of GaAs manufacturing simply was not up to the task of supplying a supercomputer. By the mid-1980s, things had changed and Cray decided it was the only way forward. Given a lack of investment on the part of large chip makers, Cray decided to invest in a GaAs chipmaking startup, GigaBit Logic, and use them as an internal supplier. Describing the system in November 1988, Cray stated that the 12 times performance increase would be made up of a three times increase due to GaAs circuits, and four times due to the use of more processors. One of the problems with the Cray-2 had been poor multiprocessing performance due to limited bandwidth between the processors, and to address this the Cray-3 would adopt the much faster architecture used in the Cray Y-MP. This would provide a design performance of 8000 MIPS, or 16 GFLOPS. Development The Cray-3 was originally slated for delivery in 1991. This was during a time when the supercomputer market was rapidly shrinking from 50% annual growth in 1980, to 10% in 1988. At