35 VUPs. This was only slightly less than the VAX 9000 mainframe's roughly 40 VUPs. In 1994, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's fifth-generation CMOS process, CMOS-5, a 0.50 µm process. It improved performance to 50 VUPs. In 1996, a 170.9 MHz NV5 was introduced, used in the VAX 7000/10000 Model 8x0. Microarchitecture The NVAX is partitioned into five semi-autonomous units, the I-box, E-box, F-box, M-box and C-box. The NVAX is macropipelined. Multiple VAX macroinstructions are processed in parallel by autonomous units, which have their own micropipelines. The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle. The E-box executes most non-floating-point instructions. It is controlled by microcode from a 1,600-word control store with the capability to patch 20 words. The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider. References Uhler, Michael G. et al. "The NVAX and NVAX+ High-performance VAX Microprocessors" . Digital Technical Journal, Volume 4, Number 3, Summer 1992. pp. 11–23. Further reading Anderson, W. (1992). "Logical verification of the NVAX CPU chip design". Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors. pp. 306–309. . Badeau, R.W. et al. (1992). "A 100-MHz macropipelined VAX microprocessor". IEEE Journal of Solid-State Circuits, Volume 27, Issue 11. pp. 1585–1598. . Fox, Thomas F. (1994). "The design of high-performance microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591. External links "NVAX" at The Computer History Simulation Project Booting a 71 MHz VAXstation 4000 Model 90 to NetBSD DEC microprocessors 32-bit microprocessors