(or return-to-zero), the request is asserted by the sender component, and the receiver responds by asserting the acknowledge; then both signals are de-asserted in turn. In a '2-phase handshaking protocol' (or transition-signalling), the requester simply toggles the value on the request wire (once), and the receiver responds by toggling the value on the acknowledge wire. Channels can also be extended to communicate data. Asynchronous datapaths Asynchronous datapaths are typically encoded using several schemes. Robust schemes use two wires or 'rails' for each bit, called 'dual-rail encoding'. In this case, first rail is asserted to transmit a 0 value, or the second rail is asserted to transmit a 1 value. The asserted rail is then reset to zero before the next data value is transmitted, thereby indicating 'no data' or a 'spacer' state. A less robust, but widely used and practical scheme, is called 'single-rail bundled data'. Here, a single-rail (i.e. synchronous-style) function block can be used, with an accompanying worst-case matched delay. After valid data inputs arrive, a request signal is asserted as the input to the matched delay. When the matched delay produces a 'done' output, the block guaranteed to have completed computation. While this scheme has timing constraints, they are simple, localized (unlike in synchronous systems), and one-sided, hence are usually easy to validate. Literature The literature in this field exists in a variety of conference and journal proceedings. The leading symposium is the IEEE Async Symposium (International Symposium on Asynchronous Circuits and Systems), founded in 1994. A variety of asynchronous papers have also been published since the mid-1980s in such conferences as IEEE/ACM Design Automation Conference, IEEE International Conference on Computer Design, IEEE/ACM International Conference on Computer-Aided Design, International Solid-State Circuits Conference, and Advanced Research in VLSI, as well as in leading journals such as IEEE Transactions on VLSI Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and Transactions on Distributed Computing. See also Design flow (EDA) Electronic design automation Integrated circuit design Isochronous timing Mesochronous network Perfect clock gating Plesiochronous system References S.M. Nowick and M. Singh, "Asynchronous Design -- Part 1: Overview and Recent Advances", IEEE Design and Test, vol. 32:3, pp. 5–18 (May/June 2015). S.M. Nowick and M. Singh, "Asynchronous Design -- Part 2: Systems and Methodologies", IEEE Design and Test, vol. 32:3, pp. 19–28 (May/June 2015) These two articles provide a broad and modern snapshot of the state-of-the-art of asynchronous