ns, however the cycle time was variable from 125 ns to 200 ns under microprogram control so that timing could be optimized. A microsequencer, based around the Am2910, directed the control flow through the microprogram. It could perform branches, loops and subroutine calls most of which could be conditional on any of several CPU status conditions. The CPU instruction decoder, decoded machine level instructions (as opposed to micro-instructions). This was achieved by using map tables held in fast parity checked RAM which mapped one byte opcodes onto micro-instruction addresses. Control was transferred to these addresses using a special sequencer operation which was performed in parallel with other CPU functions. Hence instruction decoding overlapped instruction execution. An escape mechanism was provided to allow the instruction set to be expanded beyond the 256 entries selected by any one opcode. A further mechanism existed to switch between several sets of dispatch tables, allowing the machine to support multiple instruction sets concurrently. Using this mechanism a different instruction set could be selected each time a context switch occurred. This mechanism was also used to implement privileged instruction, dynamic profiling (for performance monitoring) and multiple CPU modes (e. g. User and Kernel). The role of the cache memory, independent of the main memory, was to hold the top of an evaluation stack for a procedure oriented language. The cache had a two cycle latency after which it could deliver one word per cycle and was divided into a number of pages each with 512 32-bit words with parity protection. The pages were grouped in pairs with an architectural maximum of 16 pairs. The original machine implemented two pairs. The second member of each pair was typically used as additional fast registers and scratch storage without affecting the stack page. The lower nine bits of the CPU register, which addressed the cache, was implemented with counters and allowed increment and decrement operations (push and pop) as wells as random access. The control store The control store was built using high speed static RAMs. This was normally loaded at bootstrap time, allowing the machine to be fully user microprogrammable. The control store cycle time was 125 ns, equal to the fastest CPU cycle. The architecture allowed for up to 32 Kwords (64 bit word length) of control store however due to the limitation in memory technology the original implementation allowed a maximum of 8 Kwords. The standard