Minimal instruction set computer (MISC) is a central processing unit (CPU) architecture, usually in the form of a microprocessor, with a very small number of basic operations and corresponding opcodes, together forming an instruction set. Such sets are commonly stack-based rather than register-based to reduce the size of operand specifiers. Such a stack machine architecture is inherently simpler since all instructions operate on the top-most stack entries. One result of the stack architecture is an overall smaller instruction set, allowing a smaller and faster instruction decode unit with overall faster operation of individual instructions. Characteristics and design philosophy Separate from the stack definition of a MISC architecture, is the MISC architecture being defined by the number of instructions supported. Typically a minimal instruction set computer is viewed as having 32 or fewer instructions, where NOP, RESET, and CPUID type instructions are usually not counted by consensus due to their fundamental nature. 32 instructions is viewed as the highest allowable number of instructions for a MISC, though 16 or 8 instructions are closer to what is meant by "Minimal Instructions". A MISC CPU cannot have zero instructions as that is a zero instruction set computer. A MISC CPU cannot have one instruction as that is a one instruction set computer. The implemented CPU instructions should by default not support a wide set of inputs, so this typically means an 8-bit or 16-bit CPU. If a CPU has an NX bit, it is more likely to be viewed as being a complex instruction set computer (CISC) or reduced instruction set computer (RISC). MISC chips typically lack hardware memory protection of any kind, unless there is an application specific reason to have the feature. If a CPU has a microcode subsystem, that excludes it from being a MISC. The only addressing mode considered acceptable for a MISC CPU to have is load/store, the same as for reduced instruction set computer (RISC) CPUs. MISC CPUs can typically have between 64 KB to 4 GB of accessible addressable memory—but most MISC designs are under 1 megabyte. Also, the instruction pipelines of MISC as a rule tend to be very simple. Instruction pipelines, branch prediction, out-of-order execution, register renaming, and speculative execution broadly exclude a CPU from being classified as a MISC architecture. While 1-bit CPUs are otherwise obsolete (and were not MISCs nor OISCs), the first carbon nanotube computer is a 1-bit one-instruction set computer,