configuration had 4 Kwords on a single circuit board. Two such boards could be installed. Parity checking was provided. To achieve the required speed at reasonable cost, a two-level pipeline was employed around the control store. Later a 16 Kword board was implemented giving a maximum control store size of 32 Kwords. Main memory Main memory was organised as 32-bit words with two-way interleaving, allowing 64 bits of data to be fetched or stored in one operation. In normal operation main memory was accessed via a virtual memory management unit. In the original implementation, each main memory module contained 0.5 Mbytes of storage with parity protection constructed using 64K dynamic MOS RAMs. Random access cycle time was 500 ns per 32-bit word but multi-word transfers, for example to and from the cache, yielded an effective cycle time of 250 ns per 32-bit word (16 Mbytes per second). The memory modules decoded 26-bit physical word addresses and within this limit total memory capacity was restricted only by the number of available system bus slots; depending on the I/O configuration of the system, up to 10 Mbytes of physical memory could be installed. A later implementation of the memory module increased the size to 2 MB using 256K RAMs. Logical to physical address translation was carried out using a set of address translation tables. Each process has access to three independently extensible regions of memory, used typically for program, heap and stack. A fourth region was normally reserved for the operating system. The tables also contained a set of rights bits for each memory page giving full protection and supporting the implementation of demand paged virtual memory. The translation tables were cached in the CPU resulting, in most cases, in an overhead of only one microinstruction when performing address translation. The page size which was fixed by the hardware, was 4 Kbytes. Each logical region could be up to 256 Mbytes. The input/output subsystem The Orion I/O subsystems included a number of attached microcomputers to perform low level tasks such as running diagnostics and managing terminals and disks. The diagnostic microcomputer (based around the Zilog Z80) was embedded within the CPU. Its functions included running a system confidence check when power is first applied, bootstrapping the CPU, and taking control should an unrecoverable control store parity error be detected. It could also be used to load new microcode dynamically whilst the machine