The IBM 3705 Communications Controller is a simple computer which attaches to an IBM System/360 or System/370. Its purpose is to connect communication lines to the mainframe channel. It was a first communications controller of the popular IBM 37xx series. It was announced in March 1972. Designed for semiconductor memory which was not ready at the time of announcement, the 3705-I had to use 1.2 microsecond core storage; the later 3705-II uses 1.0 microsecond SRAM. Solid Logic Technology components, similar to those in S/370, were used. The 3705 normally occupies a single frame two feet wide and three feet deep. Up to three expansion frames can be attached for a theoretical capacity of 352 half-duplex lines and two independent channel adapters. The 3704 is an entry level version of the 3705 with limited features. Purpose IBM intended it to be used in three ways: Emulation of the older IBM 2703 Communications Controller and its predecessors. The relevant software is the Emulation Program or EP. Connection of Systems Network Architecture (SNA) devices to a mainframe. The relevant software is Network Control Program (NCP). When used in this fashion, the 3705 is considered an SNA PU4. Combining the two methods above in a configuration is called a Partitioned Emulation Program or PEP. Architecture The storage word length is 16 bits. The registers have the same width as the address bus. Their length varies between 16, 18 and 20 bits depending on the amount of storage installed. A particular interrupt level has eight registers. Register zero is the program counter which gave the address of the next instruction to be executed; the other seven are accumulators. The four odd-numbered accumulators can be addressed as eight single-byte accumulators. Instructions are fairly simple. Most are register-to-register or register-immediate instructions which execute in a single memory cycle. There are eight storage reference instructions which require two or three storage cycles to complete. The only shift capability is to shift right one or to add a register to itself. Special hardware assists in the calculation of a cyclic redundancy check for detection of transmission errors. Both CRC-16 CCITT and CRC-16 IBM are supported. Assuming the running value is maintained in storage, the execution time to accumulate one more byte is five storage cycles (three instructions). Rapid context switching was a design objective. The register file is divided into four sections. The three commonly used interrupt levels and