(EDSAC) ran its first program on May 6, 1949. The Electronic Discrete Variable Automatic Computer (EDVAC) was delivered in August 1949, but it had problems that kept it from being put into regular operation until 1951. The Commonwealth Scientific and Industrial Research Automatic Computer (CSIRAC, formerly CSIR Mk I) ran its first program in November 1949. The Standards Eastern Automatic Computer (SEAC) was demonstrated in April 1950. The Pilot ACE ran its first program on May 10, 1950 and was demonstrated in December 1950. The Standards Western Automatic Computer (SWAC) was completed in July 1950. The Whirlwind was completed in December 1950 and was in actual use in April 1951. The first ERA Atlas (later the commercial ERA 1101/UNIVAC 1101) was installed in December 1950. Design weaknesses The disadvantage of a MISC is that instructions tend to have more sequential dependencies, reducing overall instruction-level parallelism. MISC architectures have much in common with some features of some programming languages such as Forth's use of the stack, and the Java virtual machine. Both are weak in providing full instruction-level parallelism. Notable CPUs Probably the most commercially successful MISC was the original INMOS transputer architecture that had no floating-point unit. However, many 8-bit microcontrollers, for embedded computer applications, qualify as MISC. Each STEREO spacecraft includes two P24 MISC CPUs and two CPU24 MISC CPUs. See also Complex instruction set computer Reduced instruction set computer References External links Forth MISC chip designs seaForth-24 – the next to latest multi-core processor MISC design from Charles H. Moore Green Arrays - the latest multi-core processor MISC design from Charles H. Moore fa: Instruction processing Central processing unit