be stored in a 'score-boards' database to be checked later on. The checker validates that the contents of the 'score-boards' are legal. There are cases where the generator creates expected results, in addition to the inputs. In these cases, the checker must validate that the actual results match the expected ones. The arbitration manager manages all the above components together. Different coverage metrics are defined to assess that the design has been adequately exercised. These include functional coverage (has every functionality of the design been exercised?), statement coverage (has each line of HDL been exercised?), and branch coverage (has each direction of every branch been exercised?). Tools Aldec Arrow Devices Avery Design Systems: SimCluster (for parallel logic simulation) and Insight (for formal verification) Breker Verification System: Trek (a model-based test generation tool for complex SoCs) Cadence Design Systems EVE/ZeBu Mentor Graphics Nusym Technology Obsidian Software OneSpin Solutions Real Intent: Static sign-off Synopsys Valtrix Systems: Sting (a versatile design verification tool for complex SoC/CPU implementations) See also Analog verification Cleanroom software engineering High-level verification References Electronic circuit verification Logic in computer science