with error-correcting memory (ECC), the additional width of the interfaces (typically 72 rather than 64 bits) is not counted in bandwidth specifications because the extra bits are unavailable to store user data. ECC bits are better thought of as part of the memory hardware rather than as information stored in that hardware. See also CAS latency Dynamic random-access memory List of device bandwidths Memory latency Memory timings Random-access memory References General BSS Random Access Benchmark Performance Evaluation and Optimization of Random Memory Access on Multicores with High Productivity at ACM/IEEE HiPC 2010 External links STREAM Benchmark Memory Buy the Numbers Computer memory