trying to enforce some soft (recommended) design rules regarding the shapes and polygons of the physical layout of an integrated circuit. These DFM methodologies worked primarily at the full chip level. Additionally, worst-case simulations at different levels of abstraction were applied to minimize the impact of process variations on performance and other types of parametric yield loss. All these different types of worst-case simulations were essentially based on a base set of worst-case (or corner) SPICE device parameter files that were intended to represent the variability of transistor performance over the full range of variation in a fabrication process. Additionally, SPICE models should have mismatches built into them for analog circuit simulations. Many mismatches are size and orientation dependent, which can be well modeled. Always "copy exactly" when doing analog layouts as many mismatches are not well understood or controlled (i.e. if one device has North to South current flow, all matched devices should have North to South current flow). Taxonomy of yield loss mechanisms The most important yield loss models (YLMs) for VLSI ICs can be classified into several categories based on their nature. Functional yield loss is still the dominant factor and is caused by mechanisms such as misprocessing (e.g., equipment-related problems), systematic effects such as printability or planarization problems, and purely random defects. High-performance products may exhibit parametric design marginalities caused by either process fluctuations or environmental factors (such as supply voltage or temperature). The test-related yield losses, which are caused by incorrect testing, can also play a significant role. Techniques After understanding the causes of yield loss, the next step is to make the design as resistant as possible. Techniques used for this include: Substituting higher yield cells where permitted by timing, power, and routability. Changing the spacing and width of the interconnect wires, where possible Optimizing the amount of redundancy in internal memories. Substituting fault tolerant (redundant) vias in a design where possible All of these require a detailed understanding of yield loss mechanisms, since these changes trade off against one another. For example, introducing redundant vias will reduce the chance of via problems, but increase the chance of unwanted shorts. Whether this is good idea, therefore, depends on the details of the yield loss models and the characteristics of the particular design. For CNC machining Objective The objective is to design for lower cost. The cost is driven by time, so the design must