array that is capable of multiple concurrent reads and writes, and has a high-bandwidth connection to each shader array, providing the temporary storage necessary to keep the pipelines fed by having work available as much as possible. With chips such as RV530 and R580, where the number of shader units per pipeline triples, the efficiency of pixel shading drops off slightly because these shaders still have the same level of threading resources as the less endowed RV515 and R520. The next major change to the core is to its memory bus. R420 and R300 had nearly identical memory controller designs, with the former being a bug fixed release designed for higher clock speeds. R520's memory bus differs with its central controller (arbiter) that connects to the "memory clients". Around the chip are two 256-bit ring buses running at the same speed as the DRAM chips, but in opposite directions to reduce latency. Along these ring buses are four "stop" points where data exits the ring and goes into or out of the memory chips. There is a fifth, significantly less complex stop that is designed for the PCI Express interface and video input. This design allows memory accesses to be quicker though lower latency from the smaller distance the signals need to move through the GPU, and by increasing the number of banks per DRAM. The chip can spread out memory requests faster and more directly to the RAM chips. ATI claimed a 40% improvement in efficiency over older designs. Smaller cores such as RV515 and RV530 received cutbacks due to their smaller, less costly designs. RV530, for example, has two internal 128-bit buses instead. This generation has support for all recent memory types, including GDDR4. In addition to a ring bus, each memory channel has the granularity of 32-bits, which improves memory efficiency when performing small memory requests. The vertex shader engines were already at the required FP32 precision in ATI's older products. Changes necessary for SM3.0 included longer instruction lengths, dynamic flow control instructions, with branches, loops and subroutines and a larger temporary register space. The pixel shader engines are actually quite similar in computational layout to their R420 counterparts, although they were heavily optimized and tweaked to reach high clock speeds on the 90 nm process. ATI has been working for years on a high-performance shader compiler in their driver for their older hardware, so staying with