of routing. Objectives and constraints Placement is usually formulated as a problem of constrained optimization. The constraint is to remove overlaps between all the instances in the netlist. The optimization objective can be of multiple, which typically include: Total wire length: Minimizing the total wire length, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wire length (This assumes long wires have additional buffering inserted; all modern design flows do this.) Timing: The clock cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay. Congestion: While it is necessary to minimize the total wire length to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours, or make it impossible to complete all routes. Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients. A secondary objective is placement runtime minimization. Basic techniques Placement is divided into global placement and detailed placement. Global placement introduces dramatic changes by distributing all the instances to appropriate locations in the global scale with minor overlaps allowed. Detailed placement shifts each instance to nearby legal location with very moderate layout change. Placement and overall design quality is most dependent on the global placement performance. At early time, placement of integrated circuits is handled by combinatorial approaches. When IC design was of thousand-gate scale, simulated annealing methodologies such as TimberWolf exhibits the best performance. As IC design entered million-scale integration, placement was achieved by recursive hyper-graph partitioning like Capo. Quadratic placement later outperformed combinatorial solutions in both quality and stability. GORDIAN formulates the wirelength cost as a quadratic function while still spreading cells apart through recursive partitioning. The algorithm models placement density as a linear term into the quadratic cost function and solves the placement problem by pure quadratic programming. The majority of modern quadratic placers (KraftWerk, FastPlace, SimPL) follow this framework, each with different