software. It has two low power modes where the clocks to all core units are stopped, one mode exempting the data cache to maintain cache coherency with the rest of the system. Au1 is a scalar, in-order microarchitecture with a classic five stage RISC pipeline enhanced by several optimizations. It includes a 16 KiB, 4-way set associative instruction cache, a 16 KiB, 4-way, write-back, read-allocate data cache, a register file, a write buffer, and a 16/32-bit multiply-accumulate unit and 1 bit/cycle hardware divider. The cache supports prefetching by software, locking of cache lines, and a streaming mode. All pipeline stages complete in one cycle when data is available, and all pipeline hazards and dependencies are enforced by hardware interlocks. A few instructions require multiple cycles. Alchemy SoC The Au1000 SoC is rated for core frequencies up to 500 MHz. At 400 MHz it operates at 1.5 V and the chip consumes no more than 500 mW, with a performance of over 900 Dhrystone-2.1 MIPS/Watt according to Alchemy Semiconductor. Au1000 and Au1500 processors were fabricated on a TSMC 180 nm LV logic 1.5V/3.3V 1P6M process, the Au1100 reduced power consumption further with a TSMC 130 nm process. Manufacturing details of later models were not disclosed. The CPU core, the integrated memory controllers and peripherals are linked by an internal 32-bit system bus (SBUS) running at up to one half of the CPU core frequency. Slower non-bus master capable peripherals are attached with an ancillary peripheral bus. The core's data cache snoops the SBUS for coherency with other bus masters, e.g. a DMA engine. Au12xx models integrate a 64-bit side bus (RBUS) for peripherals requiring more bandwidth from the memory controller. Au13xx models have one RBUS per memory channel. All Alchemy processors integrate a DRAM controller, a static bus controller, an 8-channel DMA controller for data transfers between memory and peripherals, interrupt controllers, timers, and a power management unit. The static bus controller supports SRAM, ROM, NAND/NOR Flash (Au1550), page mode Flash/ROM, PCMCIA/CompactFlash devices, and I/O peripherals such as an external LCD controller, IDE PIO mode up to ≈80 Mbit/s (Au12xx), or ATA-6/UDMA mode 5 (Au13xx). Au1550 and later processors have a more flexible 16-channel descriptor-based DMA controller. The Au1550 integrates a SafeNet Security Engine providing an entropy-based random number generator and accelerating the DES, 3DES, AES, and RC4 encryption algorithms, and the MD5 and SHA-1 hash algorithms. Au1100 processors integrate an