FET's drain to gate. This loss of voltage gain is recovered by the upper FET. Thus, the upper transistor permits the lower FET to operate with minimal negative (Miller) feedback, improving its bandwidth. The upper FET gate is electrically grounded, so charge and discharge of the stray capacitance, Cdg, between drain and gate is simply through RD and the output load (say Rout), and the frequency response is affected only for frequencies above the associated RC time constant τ = Cdg RD//Rout, namely f = 1/(2πτ), a rather high frequency because Cdg is small. That is, the upper FET gate does not suffer from Miller amplification of Cdg. If the upper FET stage were operated alone using its source as input node (that is, common-gate (CG) configuration), it would have a good voltage gain and wide bandwidth. However, its low input impedance would limit its usefulness to very low-impedance voltage drivers. Adding the lower FET results in a high input impedance, allowing the cascode stage to be driven by a high-impedance source. If one were to replace the upper FET with a typical inductive/resistive load and take the output from the input transistor's drain (that is, a common-source (CS) configuration), the CS configuration would offer the same input impedance as the cascode, but the cascode configuration would offer a potentially greater gain and much greater bandwidth. Stability The cascode arrangement is also very stable. Its output is effectively isolated from the input both electrically and physically. The lower transistor has nearly constant voltage at both drain and source, and thus there is essentially "nothing" to feed back into its gate. The upper transistor has nearly constant voltage at its gate and source. Thus, the only nodes with significant voltage on them are the input and output, and these are separated by the central connection of nearly constant voltage and by the physical distance of two transistors. Thus in practice there is little feedback from the output to the input. Metal shielding is both effective and easy to provide between the two transistors for even greater isolation when required. This would be difficult in one-transistor amplifier circuits, which at high frequencies would require neutralization. Biasing As shown, the cascode circuit using two "stacked" FETs imposes some restrictions on the two FETs — namely, the upper FET must be biased so its source voltage is high enough (the lower FET drain voltage