used to reduce the packing size of a structure from the project default packing. This leads to interoperability problems with library headers which use, for example, , if the project packing is smaller than this. For this reason, setting the project packing to any value other than the default of 8 bytes would break the directives used in library headers and result in binary incompatibilities between structures. This limitation is not present when compiling for x86. Allocating memory aligned to cache lines It would be beneficial to allocate memory aligned to cache lines. If an array is partitioned for more than one thread to operate on, having the sub-array boundaries unaligned to cache lines could lead to performance degradation. Here is an example to allocate memory (double array of size 10) aligned to cache of 64 bytes. #include <stdlib.h> double *foo(void) { double *var;//create array of size 10 int ok; ok = posix_memalign((void**)&var, 64, 10*sizeof(double)); if (ok != 0) return NULL; return var; } Hardware significance of alignment requirements Alignment concerns can affect areas much larger than a C structure when the purpose is the efficient mapping of that area through a hardware address translation mechanism (PCI remapping, operation of a MMU). For instance, on a 32-bit operating system, a 4 KiB (4096 Bytes) page is not just an arbitrary 4 KiB chunk of data. Instead, it is usually a region of memory that's aligned on a 4 KiB boundary. This is because aligning a page on a page-sized boundary lets the hardware map a virtual address to a physical address by substituting the higher bits in the address, rather than doing complex arithmetic. Example: Assume that we have a TLB mapping of virtual address 0x2CFC7000 to physical address 0x12345000. (Note that both these addresses are aligned at 4 KiB boundaries.) Accessing data located at virtual address va=0x2CFC7ABC causes a TLB resolution of 0x2CFC7 to 0x12345 to issue a physical access to pa=0x12345ABC. Here, the 20/12-bit split luckily matches the hexadecimal representation split at 5/3 digits. The hardware can implement this translation by simply combining the first 20 bits of the physical address (0x12345) and the last 12 bits of the virtual address (0xABC). This is also referred to as virtually indexed (ABC) physically tagged (12345). A block of data of size 2(n+1) - 1 always has one sub-block of size 2n aligned on 2n bytes. This is how a