C-element built on logic gates. In particular, the so-called Maevsky's implementation is a semimodular, but non-distributive (OR-causal) circuit loosely based on. The NAND3 gate in this circuit can be replaced by two NAND2 gates. Note that Maevsky's C-element is actually a Join element, whose input signals cannot switch twice. Yet another circuit with OR-causality, which operates as a Join element. A realization of C-element on two-input gates only has been proposed by Tsirlin and then synthesized by Starodoubtsev et al. using Taxogram language This circuit coincides with that attributed (without reference) to Bartky and can operate without the input latch. Yet another version of the C-element built on two RS latches has been synthesized by Murphy using Petrify tool. However, this circuit includes inverter connected to one of the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example. Some speed-independent approaches assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist. Static and semistatic implementations In his report Muller proposed to realize C-element as a majority gate with feedback. However, to avoid hazards linked with skews of internal delays, the majority gate must have as small number of transistors as possible. Generally, C-elements with different timing assumptions can be built on AND-OR-Invert (AOI) or its dual, OR-AND-Invert (OAI) gate and inverter. Yet another option patented by Varshavsky et al. is to shunt the input signals when they are not equal each other. Being very simple, these realizations dissipate more power due to the short-circuits. Connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function: . Some simple asynchronous circuits like pulse distributors can be built solely on majority gates. Semistatic C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either or ground, and