including the same 128 registers for the procedure stack, but adding another 64 for global access. In comparison, the SPARC had 128 registers in total, and the global set was a standard window of eight. This change resulted in much better register use in the 29000 under a wide variety of workloads. The 29000 also extended the register window stack with an in-memory (and in theory, in-cache) stack. When the window filled the calls would be pushed off the end of the register stack into memory, restored as required when the routine returned. Generally, the 29000's register usage was considerably more advanced than competing designs based on the Berkeley concepts. Another difference with the Berkeley design is that the 29000 included no special-purpose condition code register. Any register could be used for this purpose, allowing the conditions to be easily saved at the expense of complicating some code. A Branch Target Cache (512 bytes on the 29000 and 1024 bytes on the 29050) stored sets of 4 or 2 sequential instructions found at the branch target address, reducing the instruction fetch latency during taken branches—the 29000 did not include any branch prediction system so there was a delay if a branch was taken. The buffer mitigated this by storing four or two instructions from the target address of the branch, which could be run instantly while the fetch buffer was re-filled with new instructions from memory. Versions The first Am29000 was released in 1988, including a built-in MMU but floating point support was offloaded to the Am29027 FPU. Units with failed MMU or Branch Target Cache were sold as the Am29005. In 1991 the line was extended with the Am29030 and Am29035, which included an 8 KB or 4 KB of instruction cache, respectively. By then the Am29050 had also become available, without on-chip cache but featuring a floating-point unit with fully pipelined multiply–accumulate operations, a larger 1 KB Branch Target Cache with a claimed 80% hit rate, and better-pipelined load operations sped up by a 4-entry TLB-like Physical Address Cache. Though it is not a superscalar processor, it permits a floating-point operation and an integer operation to complete at the same cycle. The integer and floating-point sides each have an own write port to the registers. It contained 428,000 transistors on a 1-micron process with a 0.8-micron effective channel length and was available at 20, 25, 33, and 40