Berkeley RISC is one of two seminal research projects into reduced instruction set computer (RISC) based microprocessor design taking place under the Defense Advanced Research Projects Agency VLSI Project. RISC was led by David Patterson (who coined the term RISC) at the University of California, Berkeley between 1980 and 1984. The other project took place a short distance away at Stanford University under their MIPS effort starting in 1981 and running until 1984. Berkeley's project was so successful that it became the name for all similar designs to follow; even the MIPS would become known as a "RISC processor". The Berkeley RISC design was later commercialized by Sun Microsystems as the SPARC architecture, and inspired the ARM architecture. The RISC concept Both RISC and MIPS were developed from the realization that the vast majority of programs did not use the vast majority of a processor's instructions. In a famous 1978 paper, Andrew S. Tanenbaum demonstrated that a complex 10,000 line high-level program could be represented using a simplified instruction set architecture using an 8-bit fixed-length opcode. This was roughly the same conclusion reached at IBM, whose studies of their own code running on mainframes like the IBM 360 used only a small subset of all the instructions available. Both of these studies suggested that one could produce a much simpler CPU that would still run the vast majority of real-world code. Another tidbit, not fully explored at the time, was Tanenbaum's note that 81.4 percent of the constants were either 0, 1, or 2. These realizations were taking place as the microprocessor market was moving from 8 to 16-bit with 32-bit designs about to appear. These processors were designed on the premise of trying to replicate some of the more well-respected ISAs from the mainframe and minicomputer world. For instance, the National Semiconductor NS32000 started out as an effort to produce a single-chip implementation of the VAX-11, which had a rich instruction set with a wide variety of addressing modes. The Motorola 68000 was similar in general layout. To provide this rich set of instructions, CPUs used microcode to decode the user-visible instruction into a series of internal operations. This microcode represented perhaps to of the transistors of the overall design. If, as these other papers suggested, the majority of these opcodes would never be used in practice, then this significant resource was being wasted. If one were to simply