PCI-X, short for Peripheral Component Interconnect eXtended, is a computer bus and expansion card standard that enhances the 32-bit PCI local bus for higher bandwidth demanded mostly by servers and workstations. It uses a modified protocol to support higher clock speeds (up to 133 MHz), but is otherwise similar in electrical implementation. PCI-X 2.0 added speeds up to 533 MHz, with a reduction in electrical signal levels. The slot is physically a 3.3 V PCI slot, with exactly the same size, location and pin assignments. The electrical specifications are compatible, but stricter. However, while most conventional PCI slots are the 85 mm long 32-bit version, most PCI-X devices use the 130 mm long 64-bit slot, to the point that 64-bit PCI connectors and PCI-X support are seen as synonymous. PCI-X is in fact fully specified for both 32- and 64-bit PCI connectors, and PCI-X 2.0 added a 16-bit variant for embedded applications. It has been replaced in modern designs by the similar-sounding PCI Express (officially abbreviated as PCIe), with a completely different physical connector and a very different electrical design, having one or more narrow but fast serial connection lanes instead of a number of slower connections in parallel. History Background and motivation In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. Since PCI lacks a split-response mechanism to permit the target to return data at a later time, the bus remains occupied by the target issuing retry-cycles until the read data is ready. In PCI-X, after the master issues the request, it disconnects from the PCI bus, allowing other agents to use the bus. The split-response containing the requested data is generated only when the target is ready to return all of the requested data. Split-responses increase bus efficiency by eliminating retry-cycles, during which no data can be transferred across the bus. PCI also suffered from the relative scarcity of unique interrupt lines. With only 4 interrupt pins (INT A/B/C/D), systems with many PCI devices require multiple functions to share an interrupt line, complicating host-side interrupt-handling. PCI-X added Message Signaled Interrupts, an interrupt system using writes to host-memory. In MSI-mode, the function's interrupt is not signaled by asserting an INTx line. Instead, the function performs a memory-write to a system-configured region in host-memory. Since the content and address