Interrupt (DLI) modifier bit set. (Bit 7 - $80hex/128dec) ANTIC's NMIEN register has the DLI bit set. (Bit 7 - $80hex/128dec) The Operating System vector for the Display List Interrupt (VDSLST, $0200hex/512dec) points to the starting address of the interrupt routine. Proper Setup When updating display control values care must be taken to ensure ANTIC is not currently using them. If ANTIC is processing the Display List containing an Instruction with the DLI modifier, then an interrupt could be dispatched while changing the VDSLST address, potentially crashing the system. If a Display List uses multiple interrupts, and interrupts are enabled in NMIEN after ANTIC has already passed Mode Instructions with DLI modifiers, then the Display List Interrupts will be started out of order, causing unexpected results. A reasonable sequence of events to install a Display List using Display List Interrupts: Turn off ANTIC Display List Interrupts by clearing bit 7 () of NMIEN by setting the register to value which allows the Vertical Blank Interrupt to continue running. Turn off ANTIC Display List DMA. Turn off the DMA in the Shadow register first (SDMCTL), and then if desired the same can be done to the hardware register (DMACTL). Bit 5 (value ) must be cleared, but most implementations would choose to zero all bits and then when the time comes to restart the screen restore the correct value of all bits. Set the Display List pointer Shadow address DLISTL/DLISTH to the starting address of the new Display List. Set the Display List Interrupt address VDSLST (hex/512dec) to the starting address of the interrupt routine. Wait for the next Vertical Blank Interrupt (VBI) to apply the Shadow register changes. Possible methods: Monitor RTCLOCK (//hex/18/19/20dec) for an increment indicating the VBI occurred. Monitor ANTIC's VCOUNT for changes indicating the next frame has started. Turn on ANTIC Display List Interrupts by setting bit 7 () of NMIEN. The usual value for NMIEN is which enables DLI and VBI. Turn on ANTIC Display List DMA by updating the Shadow register (SDMCTL). Bit 5 (value ) must be set, as should the bits for Playfield width, and if needed, the bits related to Player/Missile graphics. A program tightly integrated with the display cycle and aware of the electron beam position relative to the current display can bypass turning off Display List DMA. Likewise, turning off the display is not needed if the setup occurs during