and Integrity servers and offered dual-port 4Gbit/s Fibre Channel adapters, also operating at 266 MHz. AMD supported PCI-X 2.0 (266 MHz) via its 8132 Hypertransport to PCI-X 2.0 tunnel chip. ServerWorks was a vocal supporter of PCI-X 2.0 (to the detriment of the first generation PCI Express) particularly through its chief Raju Vegesna, who was however fired soon thereafter for roadmap disagreements with the Broadcom leadership. In 2003, Dell announced it would skip PCI-X 2.0 in favor of more rapid adoption of PCI Express solutions. As reported by PC Magazine, Intel began to sideline PCI-X in their 2004 roadmap, in favor of PCI Express, arguing that the latter had substantial advantages in terms of system latency and power consumption, more dramatically stated as avoiding "the 1,000-pin apocalypse" for their Tumwater chipset. Technical description PCI-X revised the conventional PCI standard by doubling the maximum clock speed (from 66 MHz to 133 MHz) and hence the amount of data exchanged between the computer processor and peripherals. Conventional PCI supports up to 64 bits at 66 MHz (though anything above 32 bits at 33 MHz is seen only in high-end systems). The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06 GB/s, compared to 133 MB/s with standard PCI. PCI-X also improves the fault tolerance of PCI, allowing, for example, faulty cards to be reinitialized or taken offline. PCI-X is backward compatible to PCI in the sense that the entire bus falls back to PCI if any card on the bus does not support PCI-X. The two most fundamental changes are: The shortest time between a signal appearing on the PCI bus and a response to that signal occurring on the bus has been extended to 2 cycles, rather than 1. This allows much faster clock rates, but causes many protocol changes: The ability of the conventional PCI bus protocol to insert wait states on any cycle based on the IRDY# and TRDY# signals has been deleted; PCI-X only allows bursts to be interrupted at 128-byte boundaries. The initiator must deassert FRAME# two cycles before the end of the transaction. The initiator may not insert wait states. The target may, but only before any data is transferred, and wait states for writes are limited to multiples of 2 clock cycles. Likewise, the length of a burst is decided before it begins; it may not be halted on