the last few were laid off in January 2006. The company name was attributed to Tom Riordan. He believed that the company would survive to the age when semiconductor geometry dimensions would become so small that quantum effects would dominate circuit behavior. Devices The first QED microprocessor was the R4600. The founders of QED, who were previously involved with the R4000, felt that the large device was too complicated and that a simpler implementation would give a better price/performance ratio. For that reason, the R4600 is a re-implementation of the 5-stage Classic RISC pipeline with large (for the time) caches. For a while, this small and low cost device was one of the highest performance microprocessors on the market. While the initial target market of a MIPS laptop computer never materialized, this device found success in several markets. It was the first RISC processor used within a Cisco Systems network router. It was used in several Atari/Midway arcade games such as the well-known original Mortal Kombat game. The R4600 was licensed by IDT and Toshiba who manufactured and sold the devices. The R4700 was targeted at SGI, who wanted a little more floating point performance. The R4700 improved on the repeat rate of floating point multiply instructions. This device was used inside the SGI Indy low-end workstation. The R4700 was licensed by IDT and Toshiba who manufactured and sold the devices. The R4650 was commissioned by NKK, who desired a cheaper implementation for a video console game machine. The R4650 achieved a smaller die area by cutting the caches in half, only implementing single precision floating-point. This device was the first QED device that implemented the multiply–accumulate instructions, which enabled software functions such as softmodem. This device was used in the original Microsoft WebTV device. The R4650 was licensed by IDT and NKK who manufactured and sold the devices. The R4640 was the same chip but with the system bus restricted to 32-bits instead of 64-bits. The R5000 was commissioned by SGI. This device doubled the instruction and data caches to 32 KB. It implemented a high-performance, fully pipelined floating point unit with multiply–accumulate capability and a SRT divider. The device had a limited implementation of superscalar instruction issue in which one integer instruction and one floating-point instruction could be issued in one cycle. This device was used in the SGI O2 and SGI Indy low-end workstations. The design was