is straightforward to code the simple cases of this optimization, keeping all the details correct as the code is replicated and transformed is an error-prone process. The above loop will only achieve 80% of peak flops on the example system when blocked for the 16KB L1 cache size. It will do worse on systems with even more unbalanced memory systems. Fortunately, the Pentium 4 has 256KB (or more, depending on the model) high-bandwidth level-2 cache as well as the level-1 cache. There is a choice: Adjust the block sizes for the level-2 cache. This will stress the processor's ability to keep many instructions in flight simultaneously, and there is a good chance it will be unable to achieve full bandwidth from the level-2 cache. Block the loops again, again for the level-2 cache sizes. With a total of three levels of blocking (for the register file, for the L1 cache, and the L2 cache), the code will minimize the required bandwidth at each level of the memory hierarchy. Unfortunately, the extra levels of blocking will incur still more loop overhead, which for some problem sizes on some hardware may be more time-consuming than any shortcomings in the hardware's ability to stream data from the L2 cache. Rather than specifically tune for one particular cache size, as in the first example, a cache-oblivious algorithm is designed to take advantage of any available cache, no matter what its size is. This automatically takes advantage of two or more levels of memory hierarchy, if available. Cache-oblivious algorithms for matrix multiplication are known. See also Duff's device Loop optimization References Further reading Wolfe, M. More Iteration Space Tiling. Supercomputing'89, pages 655–664, 1989. Wolf, M. E. and Lam, M. A Data Locality Optimizing Algorithm. PLDI'91, pages 30–44, 1991. Irigoin, F. and Triolet, R. Supernode Partitioning. POPL'88, pages 319–329, 1988. Xue, J. Loop Tiling for Parallelism. Kluwer Academic Publishers. 2000. M. S. Lam, E. E. Rothberg, and M. E. Wolf. The cache performance and optimizations of blocked algorithms. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 63–74, April 1991. External links Streams benchmark results, showing the overall balance between floating point operations and memory operations for many different computers "CHiLL: Composable High-Level Loop Transformation Framework" Compiler optimizations Articles with example C code