owned by SGI, which licensed the design to IDT and NEC and eventually to Toshiba. The PowerPC 603q was commissioned by Motorola and the target market was Apple Computer's low-cost accounts including a home computer for students and a home video console game named Pippen. The 603q was basically the R4600 pipeline re-targeted for the PowerPC instruction set. Since the PowerPC 603 was then the most power-efficient chip from the AIM alliance, the name of this device was chosen to reflect its low-cost and low-power characteristics. Once those Apple projects were cancelled, Motorola stopped the development of the 603q even though QED had received first silicon samples and they were functional. The RM52XX series was the first product line sold directly by QED. The first of the series was a cost-reduced version of the R5000 with smaller caches and a different pin-out. The earlier RM52X0 devices had only 16 KB caches while the later RM52X1 devices had 32 KB caches. The RM523X devices had 32-bit system buses while RM526X had 64-bit system buses. This product line was very successful in the laser printer market, winning many accounts at printer companies such as Hewlett-Packard, Lexmark, Ricoh, Samsung. The RM70XX series was the second product line sold directly by QED. It implemented a large 256 KB on-chip level 2 cache. The RM7000 was one of the first microprocessors to do so, especially within the embedded microprocessor market segment. It also implemented symmetric superscalar instruction issue with two integer execution units. The RM7061 device was a pin-compatible upgrade for the RM526X series. This product line was a very successful follow-on to the RM52XX products. The RM9x00 family was the first SOC implemented by QED. The Apollo microprocessor core that was part of the RM9x00 had its pipeline lengthened to 7 stages to enable higher operating frequencies. Dynamic branch prediction was added to ameliorate the longer branch latencies. Within the RM9x00, two Apollo cores were used to implement a dual-core device. These processor cores successfully achieved their operating frequency target of 1 GHz. The SOC system interconnect was an in-house design with centralized storage for the transactions flowing through the SOC. Peripherals included a DDR memory controller, a SysAD bus controller, a boot bus controller, a DMA controller and a Hypertransport controller. A second generation device added a Gigabit Ethernet controller, a PCI controller and cache coherency. This product family was not successful due