absolute indexed with auto-increment, and absolute indexed with auto-decrement, both direct and indirect The most significant bit of all relative and absolute addresses is used to indicate indirection. The only exceptions are where the opcodes of meaningless operations are used for other purposes: the opcode for AND register zero with register zero is used for the HALT instruction. the opcode for STORE register zero into register zero is used for the NOP instruction. Although the instruction LOAD register zero with register zero would appear meaningless, and was officially unsupported, it did set the condition code and was often used to determine the status of this register.. The Signetics Assembler generated code as if it was the instruction IORZ,R0 instead. Indexing With all arithmetic and logical instructions using absolute (direct) addressing, bits 14 and 13 of the address field are used to indicate the indexing mode as follows: 00 no indexing 01 indexing with auto increment 10 indexing with auto decrement 11 indexing only When indexing is specified, the register defined in the instruction becomes the index register, and the source/destination is implicitly Register zero. For indirect indexing, Post indexing is used, i.e. the indirect address is first fetched from memory and then the index is added to it. Branching Probably the most mini-computer like aspect of the 2650 is the enormous number (62) of branch (jump) instructions; all these instructions could also use indirection: BIRR and BIRA: Increment register and branch if non-zero (R0, R1, R2 or R3) with relative or absolute addressing BDRR and BDRA: Decrement register and branch if non-zero (R0, R1, R2 or R3) with relative or absolute addressing BRNR and BRNA: branch if register non-zero (R0, R1, R2 or R3) with relative or absolute addressing BCTR and BCTA: branch on condition True (zero, greater-than, less-than or unconditional) with relative or absolute addressing BCFR and BCFA: branch on condition False (zero, greater-than or less-than) with relative or absolute addressing. ZBRR: branch relative to address zero BXA: branch indexed Like the Intel 8080, the 2650 had instructions to conditionally branch to, and return from, a subroutine: BSTR and BSTA: branch to subroutine on condition True (zero, greater-than, less-than or unconditional) with relative or absolute addressing BSFR and BSFA: branch to subroutine on condition False (zero, greater-than or less-than) with relative or absolute addressing BSNR and BSNA: branch to subroutine if register non-zero (R0, R1, R2 or R3) with