are less of an issue. Electromigration in metallic interconnect and ESD damage to the tiny components are also of concern. Finally, the physical layout of certain circuit subblocks is typically critical, in order to achieve the desired speed of operation, to segregate noisy portions of an IC from quiet portions, to balance the effects of heat generation across the IC, or to facilitate the placement of connections to circuitry outside the IC. Design flow A typical IC design cycle involves several steps: System Specification Feasibility study and die size estimate Function analysis Architectural or System Level Design Logic Design Analogue Design, Simulation & Layout Digital Design & Simulation System Simulation, Emulation & Verification Circuit Design Digital design synthesis Design For Test and Automatic test pattern generation Design for manufacturability (IC) Physical Design Floorplanning Place and Route Parasitic Extraction Physical Verification & Signoff Static timing Co-simulation and timing Mask data preparation (Layout Post Processing) Chip finishing with Tape out Reticle layout Layout-to-mask preparation Reticle fabrication Photomask fabrication Wafer fabrication Packaging Die test Post silicon validation and integration Device characterization Tweak (if necessary) Chip Deployment Datasheet generation (of usually a Portable Document Format (PDF) file) Ramp up Production Yield Analysis / Warranty Analysis Reliability (semiconductor) Failure analysis on any returns Plan for next generation chip using production information if possible Summary Roughly saying, digital IC design can be divided into three parts. Electronic system-level design: This step creates the user functional specification. The user may use a variety of languages and tools to create this description. Examples include a C/C++ model, VHDL, SystemC, SystemVerilog Transaction Level Models, Simulink, and MATLAB. RTL design: This step converts the user specification (what the user wants the chip to do) into a register transfer level (RTL) description. The RTL describes the exact behavior of the digital circuits on the chip, as well as the interconnections to inputs and outputs. Physical circuit design: This step takes the RTL, and a library of available logic gates (standard cell library), and creates a chip design. This step involves use of IC layout editor, layout and floor planning, figuring out which gates to use, defining places for them, and wiring (clock timing synthesis, routing) them together. Note that the second step, RTL design, is responsible for the chip doing the right thing. The third step, physical design, does not affect the functionality at all (if done correctly) but determines how