2.6 blacklisted any ACPI BIOS from before January 1, 2001. Linux-based operating systems can provide handling of ACPI events via acpid. OSPM responsibilities Once an OSPM-compatible operating system activates ACPI, it takes exclusive control of all aspects of power management and device configuration. The OSPM implementation must expose an ACPI-compatible environment to device drivers, which exposes certain system, device and processor states. Power states Global states The ACPI Specification defines the following four global "Gx" states and six sleep "Sx" states for an ACPI-compliant computer system: The specification also defines a Legacy state: the state of an operating system which does not support ACPI. In this state, the hardware and power are not managed via ACPI, effectively disabling ACPI. Device states The device states D0–D3 are device dependent: D0 or Fully On is the operating state. As with S0ix, Intel has D0ix states for intermediate levels on the SoC. D1 and D2 are intermediate power-states whose definition varies by device. D3: The D3 state is further divided into D3 Hot (has auxiliary power), and D3 Cold (no power provided): Hot: A device can assert power management requests to transition to higher power states. Cold or Off has the device powered off and unresponsive to its bus. Processor states The CPU power states C0–C3 are defined as follows: C0 is the operating state. C1 (often known as Halt) is a state where the processor is not executing instructions, but can return to an executing state essentially instantaneously. All ACPI-conformant processors must support this power state. Some processors, such as the Pentium 4 and AMD Athlon, also support an Enhanced C1 state (C1E or Enhanced Halt State) for lower power consumption, however this proved to be buggy on some systems. C2 (often known as Stop-Clock) is a state where the processor maintains all software-visible state, but may take longer to wake up. This processor state is optional. C3 (often known as Sleep) is a state where the processor does not need to keep its cache coherent, but maintains other state. Some processors have variations on the C3 state (Deep Sleep, Deeper Sleep, etc.) that differ in how long it takes to wake the processor. This processor state is optional. Additional states are defined by manufacturers for some processors. For example, Intel's Haswell platform has states up to C10, where it distinguishes core states and package states. Performance state While a device or