had thirty-two 32-bit general-purpose registers, with the last three of them commonly used as stack pointer, frame pointer, and argument pointer, which well matched high level language compilers' calling conventions. The V60 and V70 have 119 machine instructions, with that number being extended slightly to 123 instructions for the V80. The instructions are of non-uniform length, between one and 22 bytes, and take two operands, both of which can be addresses in main memory. After studying the V60's reference manual, Paul Vixie described it as "a very VAX-ish arch, with a V20/V30 emulation mode (which[...] means it can run Intel 8086/8088 software)". The V60–V80 has a built-in memory management unit (MMU) that divides a 4-GB virtual address space into four 1-GB sections, each section being further divided into 1,024 1-MB areas, and each area being composed of 256 4-KB pages. On the V60/V70, four registers (ATBR0 to ATBR3) store section pointers, but the "area tables entries" (ATE) and page tables entries (PTE) are stored in off-chip RAM. The V80 merged the ATE and ATBR registers—which are both on-chip, with only the PTE entries stored in external RAM—allowing for faster execution of translation lookaside buffer (TLB) misses by eliminating one memory read. The translation lookaside buffers on the V60/70 are 16-entry fully associative with replacement done by microcode. The V80, in contrast, has a 64-entry 2-way set associative TLB with replacement done in hardware. TLB replacement took 58 cycles in the V70 and disrupted the pipelined execution of other instructions. On the V80, a TLB replacement takes only 6 or 11 cycles depending on whether the page is in the same area; pipeline disruption no longer occurs in the V80 because of the separate TLB replacement hardware unit, which operates in parallel with the rest of the processor. All three processors use the same protection mechanism, with 4 protection levels set via a program status word, Ring 0 being the privileged level that could access a special set of registers on the processors. All three models support a triple-mode redundancy configuration with three CPUs used in a byzantine fault–tolerance scheme with bus freeze, instruction retry, and chip replacement signals. The V80 added parity signals to its data and address buses. String operations were implemented in microcode in the V60/V70; but these were aided by a hardware data control unit, running at full bus speed, in the V80. This made string operations