In electronics, a multi-transistor configuration called the Darlington configuration (commonly called a Darlington pair) is a circuit consisting of two bipolar transistors with the emitter of one transistor connected to the base of the other, such that the current amplified by the first transistor is amplified further by the second one. The collectors of both transistors are connected together. This configuration has a much higher current gain than each transistor taken separately. It acts like and is often packaged as a single transistor. It was invented in 1953 by Sidney Darlington. Behavior A Darlington pair behaves like a single transistor, meaning it has one base, collector, and emitter. It typically creates a high current gain (approximately the product of the gains of the two transistors, due to the fact that their β values multiply together). A general relation between the compound current gain and the individual gains is given by: If β1 and β2 are high enough (hundreds), this relation can be approximated with: Advantages A typical Darlington transistor has a current gain of 1000 or more, so that only a small base current is needed to make the pair switch on much higher switched currents. Another advantage involves providing a very high input impedance for the circuit which also translates into an equal decrease in output impedance. The ease of creating this circuit also provides an advantage. It can be simply made with two separate NPN (or PNP) transistors, and is also available in a variety of single packages. Disadvantages One drawback is an approximate doubling of the base–emitter voltage. Since there are two junctions between the base and emitter of the Darlington transistor, the equivalent base–emitter voltage is the sum of both base–emitter voltages: For silicon-based technology, where each VBEi is about 0.65 V when the device is operating in the active or saturated region, the necessary base–emitter voltage of the pair is 1.3 V. Another drawback of the Darlington pair is its increased "saturation" voltage. The output transistor is not allowed to saturate (i.e. its base–collector junction must remain reverse-biased) because the first transistor, when saturated, establishes full (100%) parallel negative feedback between the collector and the base of the second transistor. Since collector–emitter voltage is equal to the sum of its own base–emitter voltage and the collector-emitter voltage of the first transistor, both positive quantities in normal operation, it always exceeds the base-emitter voltage. (In symbols,