memory but an updated version was later released which can use DDR4. Purpose Memory controllers contain the logic necessary to read and write to DRAM, and to "refresh" the DRAM. Without constant refreshes, DRAM will lose the data written to it as the capacitors leak their charge within a fraction of a second (not more than 64 milliseconds according to JEDEC standards). Reading and writing to DRAM is performed by selecting the row and column data addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM uses the converted inputs to select the correct memory location and return the data, which is then passed back through a multiplexer to consolidate the data in order to reduce the required bus width for the operation. Bus width is the number of parallel lines available to communicate with the memory cell. Memory controllers' bus widths range from 8-bit in earlier systems, to 512-bit in more complicated systems and video cards (typically implemented as four 64-bit simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a 128-bit memory device). Some memory controllers, such as the one integrated into PowerQUICC II processors, include error detection and correction hardware. Security A few experimental memory controllers (mostly aimed at the server market where data protection is legally required) contain a second level of address translation, in addition to the first level of address translation performed by the CPU's memory management unit. Memory controllers integrated into certain Intel Core processors also provide memory scrambling as a feature that turns user data written to the main memory into pseudo-random patterns. Memory Scrambling (in Cryptographic Theory) is supposed to prevent forensic and reverse-engineering analysis based on DRAM data remanence by effectively rendering various types of cold boot attacks ineffective. In current practice this has not been achieved. However Memory Scrambling has only been designed to address DRAM-related electrical problems. The late 2010s Memory Scrambling Standards do not fix or prevent security issues or problems. The 2010s Memory Scrambling standards are not cryptographically secure, or necessarily open sourced or open to public revision or analysis. ASUS and Intel have their own memory scrambling standards. Currently ASUS motherboards have allowed the user to choose which memory scrambling standards to use [ASUS or Intel] or whether to turn the feature