3.4, 3.4, and 3.6 GHz clock frequency). All steppings of Presler models 915, 920, 925, 930, and 935, as well as the C1, D0 steppings of 940, 945 featured a 95 watt TDP. All other models (i.e. certain models with 3.2 GHz or faster clock frequencies) were rated at 130 watt — a 37% increase in power consumption. [*] The first batch of Presler processors (revision B1) had the EIST feature turned off by a microcode update because of stability issues. That affected only its power consumption, when idle, and thermal dissipation. Chips with working EIST started shipping in Q2 2006. They had a different S-Spec number which can be found in Intel errata documentation. Presler XE The Pentium Extreme Edition based on the dual-core Pentium D branded Presler was introduced as the 955 model, at 3.46 GHz, and used a 1066 MT/s FSB compared to the 800 MT/s in the non-Extreme edition. A second version, the 965 at 3.73 GHz followed in March 2006. Both CPUs also feature Hyper-Threading Technology and an unlocked multiplier. Overclockers have been able to overclock the core to 4.26 GHz using air cooling simply by raising the unlocked CPU multiplier. The 'Presler Extreme Edition' was intended to only be combined with the Intel 975X chipset, it could also work with the 955X chipset, though this combination was not supported by Intel. The i975X featured the ICH7R southbridge and supported all LGA 775 (Socket T) Pentium 4, Pentium D, and Pentium Extreme Edition branded processors. Successor The Pentium D brand was merged with the Pentium 4 brand and succeeded on July 27, 2006, by the Core 2 branded line of processors with the Core microarchitecture released as dual- and quad-core processors branded Duo, Quad, and Extreme. Implementation In a single-processor scenario, the CPU-to-northbridge link is point-to-point and the only real requirement is that it is fast enough to keep the CPU fed with data from memory. When assessing the Pentium D, it is important to note that it is essentially two CPUs in the same package and that it will face the same bus contention issues as a pair of Xeons prior to the Dual Independent Bus architecture introduced with the Dual-Core Dempsey Xeons. To use a crude analogy one could say that instead of using a single cable between CPU and north bridge, one must use a Y-splitter. Leaving aside advanced issues such as