benefit of cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width. This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins. The device had a 35 nm channel width and 70 nm channel length. The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at the University of California, Berkeley to develop a deep sub-micron transistor based on DELTA technology. The group was led by Hisamoto along with TSMC's Chenming Hu. The team made the following breakthroughs between 1998 and 2004. 1998 N-channel FinFET (17 nm) Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor, Wen-Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya Asano 1999 P-channel FinFET (sub-50 nm) Digh Hisamoto, Chenming Hu, Xuejue Huang, Wen-Chin Lee, Charles Kuo, Leland Chang, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi 2001 15 nm FinFET Chenming Hu, Yang-Kyu Choi, Nick Lindert, P. Xuan, S. Tang, D. Ha, Erik Anderson, Tsu-Jae King Liu, Jeffrey Bokor 2002 10 nm FinFET Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor, David Kyser, Chenming Hu, Tsu-Jae King Liu, Bin Yu, Leland Chang 2004 High-κ/metal gate FinFET D. Ha, Hideki Takeuchi, Yang-Kyu Choi, Tsu-Jae King Liu, W. Bai, D.-L. Kwong, A. Agarwal, M. Ameen They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper, used to describe a non-planar, double-gate transistor built on an SOI substrate. In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology. In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates. In 2020, Chenming Hu received the IEEE Medal of Honor award for his development of the FinFET, which the Institute of Electrical and Electronics Engineers (IEEE) credited with taking transistors to the third dimension and extending Moore's law. Commercialization The industry's first 25 nanometer