The RapidIO architecture is a high-performance packet-switched electrical connection technology. RapidIO supports messaging, read/write and cache coherency semantics. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect. History The RapidIO protocol was originally designed by Mercury Computer Systems and Motorola (Freescale) as a replacement for Mercury's RACEway proprietary bus and Freescale's PowerPC bus. The RapidIO Trade Association was formed in February 2000, and included telecommunications and storage OEMs as well as FPGA, processor, and switch companies. Releases The RapidIO specification revision 1.1 (3xN Gen1), released in March 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption. The RapidIO specification revision 1.2, released in June 2002, defined a serial interconnect based on the XAUI physical layer. Devices based on this specification achieved significant commercial success within wireless baseband, imaging and military compute. The RapidIO specification revision 1.3 was released in June 2005. The RapidIO specification revision 2.0 (6xN Gen2), was released in March 2008, added more port widths (2×, 8×, and 16×) and increased the maximum lane speed to 6.25 GBd / 5 Gbit/s. Revision 2.1 has repeated and expanded the commercial success of the 1.2 specification. The RapidIO specification revision 2.1 was released in September 2009. The RapidIO specification revision 2.2 was released in May 2011. The RapidIO specification revision 3.0 (10xN Gen3), was released in October 2013, has the following changes and improvements compared to the 2.x specifications: Based on industry-standard Ethernet 10GBASE-KR electrical specifications for short (20 cm + connector) and long (1 m + 2 connector) reach applications Directly leverages the Ethernet 10GBASE-KR DME training scheme for long-reach signal quality optimization Defines a 64b/67b encoding scheme (similar to the Interlaken standard) to support both copper and optical interconnects and to improve bandwidth efficiency Dynamic asymmetric links to save power (for example, 4× in one direction, 1× in the other) Addition of a time synchronization capability similar to IEEE 1588, but much less expensive to implement Support for 32-bit device IDs, increasing maximum system size and enabling innovative hardware virtualization support Revised routing table programming model simplifies network management software Packet exchange protocol optimizations The RapidIO specification revision 3.1, was released in October 2014, was developed through a collaboration between the RapidIO Trade Association and NGSIS. Revision 3.1 has the following enhancements compared to the 3.0 specification: MECS Time Synchronization protocol