for smaller embedded systems. MECS Time Synchronization supports redundant time sources. This protocol is lower cost than the Timestamp Synchronization Protocol introduced in revision 3.0 PRBS test facilities and standard register interface. Structurally Asymmetric Link behavioral definition and standard register interface. Structurally Asymmetric Links carry much more data in one direction than the other, for applications such as sensors or processing pipelines. Unlike dynamic asymmetric links, Structurally Asymmetric Links allow implementers to remove lanes on boards and in silicon, saving size, weight, and power. Structurally asymmetric links also allow the use of alternative lanes in the case of a hardware failure on a multi-lane port. Extended error log to capture a series of errors for diagnostic purposes Space device profiles for endpoints and switches, which define what it means to be a space-compliant RapidIO device. The RapidIO specification revision 3.2 was released in February 2016. The RapidIO specification revision 4.0 (25xN Gen4) was released in June 2016. has the following changes and improvements compared to the 3.x specifications: Support 25 Gbaud lane rate and physical layer specification, with associated programming model changes Allow IDLE3 to be used with any Baud Rate Class, with specified IDLE sequence negotiation Increased maximum packet size to 284 bytes in anticipation of Cache Coherency specification Support 16 physical layer priorities Support “Error Free Transmission” for high throughput isochronous information transfer The RapidIO specification revision 4.1 was released in July 2017. Wireless infrastructure RapidIO fabrics are used in cellular infrastructure 3G, 4G and LTE networks with millions of RapidIO ports shipped into wireless base stations worldwide. RapidIO fabrics were originally designed to support connecting different types of processors from different manufacturers together in a single system. This flexibility has driven the widespread use of RapidIO in wireless infrastructure equipment where there is a need to combine heterogeneous, DSP, FPGA and communication processors together in a tightly coupled system with low latency and high reliability. Data centers Data center and HPC analytics systems have been deployed using a RapidIO 2D Torus Mesh Fabric, that provides a high speed general purpose interface among the system cartridges for applications that benefit from high bandwidth, low latency node-to-node communication. The RapidIO 2D Torus unified fabric is routed as a torus ring configuration connecting up to 45 server cartridges capable of providing 5Gbs per lane connections in each direction to its north, south, east and west neighbors. This allows the system