to meet many unique HPC applications where efficient localized traffic is needed. Also, using an open modular data center and compute platform, a heterogeneous HPC system has showcased the low latency attribute of RapidIO to enable real-time analytics. In March 2015 a top-of-rack switch was announced to drive RapidIO into mainstream data center applications. Aerospace The interconnect or "bus" is one of the critical technologies in the design and development of spacecraft avionic systems that dictates its architecture and level of complexity. There are a host of existing architectures that are still in use given their level of maturity. These existing systems are sufficient for a given type of architecture need and requirement. Unfortunately, for next generation missions a more capable avionics architecture is desired; which is well beyond the capabilities levied by existing architectures. A viable option toward the design and development of these next generation architectures is to leverage existing commercial protocols capable of accommodating high levels of data transfer. In 2012, RapidIO was selected by the Next Generation Spacecraft Interconnect Standard (NGSIS) working group to serve as the foundation for standard communication interconnects to be used in spacecraft. The NGSIS is an umbrella standards effort that includes RapidIO Version 3.1 development, and a box level hardware standards effort under VITA 78 called SpaceVPX or High ReliabilityVPX. The NGSIS requirements committee developed extensive requirements criteria with 47 different elements for the NGSIS interconnect. Independent trade study results by NGSIS member companies demonstrated the superiority of RapidIO over other existing commercial protocols, such as InfiniBand, Fibre Channel, and 10G Ethernet. As a result, the group decided that RapidIO offered the best overall interconnect for the needs of next-generation spacecraft. PHY roadmap The RapidIO roadmap aligns with Ethernet PHY development. RapidIO specifications for 50 GBd and higher links are under investigation. Terminology Link Partner One end of a RapidIO link. Endpoint A device that can originate and/or terminate RapidIO packets. Processing Element A device which has at least one RapidIO port Switch A device that can route RapidIO packets. Protocol overview The RapidIO protocol is defined in a 3-layered specification: Physical: Electrical specifications, PCS/PMA, link-level protocol for reliable packet exchange Transport: Routing, multicast, and programming model Logical: Logical I/O, messaging, global shared memory (CC-NUMA), flow control, data streaming System specifications include: System Initialization Error Management/Hot Swap Physical layer The RapidIO electrical specifications are based on industry-standard Ethernet and Optical Interconnect