input, X)," & "544 (bc_1, *, control, 1)," & "545 (bc_1, GPIO50_ATACS0, output3, X, 544, 1, Z)," & "546 (bc_1, GPIO50_ATACS0, input, X)," & That shows two balls on a mid-size chip (the boundary scan includes about 620 such lines, in a 361-ball BGA package), each of which has three components in the BSR: a control configuring the ball (as input, output, what drive level, pullups, pulldowns, and so on); one type of output signal; and one type of input signal. There are JTAG instructions to SAMPLE the data in that boundary scan register, or PRELOAD it with values. During testing, I/O signals enter and leave the chip through the boundary-scan cells. Testing involves a number of test vectors, each of which drives some signals and then verifies that the responses are as expected. The boundary-scan cells can be configured to support external testing for interconnection between chips (EXTEST instruction) or internal testing for logic within the chip (INTEST instruction). Board test infrastructure Typically high-end commercial JTAG testing systems allow the import of design 'netlists' from CAD/EDA systems plus the BSDL models of boundary scan/JTAG compliant devices to automatically generate test applications. Common types of test include Scan-path 'infrastructure' or integrity Boundary-scan device pin to boundary-scan device pin 'interconnect' Boundary-scan pin to memory device or device cluster (SRAM, DRAM, DDR etc.) Arbitrary logic cluster testing When used during manufacturing, such systems also support non-test but affiliated applications such as in-system programming of various types of flash memory: NOR, NAND, and serial (I2C or SPI). Such commercial systems are used by board test professionals and will often cost several thousand dollars for a fully-fledged system. They can include diagnostic options to accurately pin-point faults such as open circuits and shorts and may also offer schematic or layout viewers to depict the fault in a graphical manner. Tests developed with such tools are frequently combined with other test systems such as in-circuit testers (ICTs) or functional board test systems. Debugging The boundary scan architecture also provides functionality which helps developers and engineers during development stages of an embedded system. A JTAG Test Access Port (TAP) can be turned into a low-speed logic analyzer. History James B. Angell at Stanford University proposed serial testing. IBM developed level-sensitive scan design (LSSD). See also AOI Automated optical inspection AXI Automated x-ray inspection ICT In-circuit test Functional testing (see Acceptance testing) JTAG References External links Official