is a wide instruction that operates on one or more fields of the PHV and data to support this instruction. The output PHV is then sent to the next MA stage or to the deparser. The deparser takes in the PHV as well as the original packet and it's metadata (to fill in missing bits that weren't extracted into the PHV) and then outputs the modified packet as chunks. It's typically programmable as with the parser and may reuse some of the configuration files. FlexNIC attempts to apply this model to Network Interface Controllers allowing servers to send and receive packets at high speeds while maintaining protocol flexibility and without increasing the CPU overhead. Generic functions In the generic role as a packet processor, a number of optimised features or functions are typically present in a network processor, which include: Pattern matching – the ability to find specific patterns of bits or bytes within packets in a packet stream. Key lookup – the ability to quickly undertake a database lookup using a key (typically an address in a packet) to find a result, typically routing information. Computation Data bitfield manipulation – the ability to change certain data fields contained in the packet as it is being processed. Queue management – as packets are received, processed and scheduled to be sent onwards, they are stored in queues. Control processing – the micro operations of processing a packet are controlled at a macro level which involves communication and orchestration with other nodes in a system. Quick allocation and re-circulation of packet buffers. Architectural paradigms In order to deal with high data-rates, several architectural paradigms are commonly used: Pipeline of processors - each stage of the pipeline consisting of a processor performing one of the functions listed above. Parallel processing with multiple processors, often including multithreading. Specialized microcoded engines to more efficiently accomplish the tasks at hand. With the advent of multicore architectures, network processors can be used for higher layer (L4-L7) processing. Additionally, traffic management, which is a critical element in L2-L3 network processing and used to be executed by a variety of co-processors, has become an integral part of the network processor architecture, and a substantial part of its silicon area ("real estate") is devoted to the integrated traffic manager. Modern network processors are also equipped with low-latency high-throughput on-chip interconnection networks optimized for the exchange of small messages among cores