PC are preserved. For short-distance branches, there are 63 1-byte instructions which perform PC-relative branches from PC−32 to PC+31. This is a 15-bit addition, and no page boundary requirements apply. Conditional branches per se do not exist, nor does the processor provide the traditional ZCVN status flags, although the program status word contains carry and half-carry flags for multi-byte arithmetic. Rather, there are a number of compare-and-skip instructions. For example, compares its two operands, and skips the following instruction if they are unequal. Any instruction may be skipped; it is not limited to branches. A feature unique to the COP8 architecture is the instruction. This compares the low 4 bits of the B (memory pointer) register with a 4-bit immediate constant, and can be used to loop until B has reaches the end of a small (up to 16 byte) buffer. An interesting extension of this mechanism is the return-and-skip instruction, which lets any subroutine call conditionally skip the following instruction. This provides a very compact way to return a boolean value from a subroutine. Instruction set COP8 operands are listed in destination, source order. Most instructions have the accumulator A as one of the operands. The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or , the RAM address selected by the B register. Some instructions also support RAM addressing by the X register (), and post-inc/decrement variants (, , , ). Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed. On the other hand, absolute RAM addressing is not directly encoded in most cases. Rather, a special "direct addressing" prefix opcode, followed by a 1-byte address, may precede any instruction with a operand, and changes it to a memory direct operand. This adds two bytes and three cycles to the instruction. (Conditional-skip instructions skip the prefix and following instruction as a pair.) All "move" instructions are called (load) even if the destination is a memory address. Unusually, there are no instructions with the accumulator as a source; stores are done with the instruction which exchanges the accumulator with the memory operand, storing A and loading the previous memory contents. (This takes no additional time; is a one-cycle instruction.) There are instructions to fetch from tables in ROM. These combine the high 7 bits of the program counter (PCU) with the accumulator,