especially home computers, refresh was often handled by the video circuitry as it often had to read from large areas of memory, and performed refreshes as part of these operations. CAS before RAS refresh For convenience, the counter was quickly incorporated into the DRAM chips themselves. If the line is driven low before (normally an illegal operation), then the DRAM ignores the address inputs and uses an internal counter to select the row to open. This is known as -before- (CBR) refresh. This became the standard form of refresh for asynchronous DRAM, and is the only form generally used with SDRAM. Hidden refresh Given support of -before- refresh, it is possible to deassert while holding low to maintain data output. If is then asserted again, this performs a CBR refresh cycle while the DRAM outputs remain valid. Because data output is not interrupted, this is known as hidden refresh. Page mode DRAM Page mode DRAM is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In Page mode DRAM, after a row was opened by holding low, the row could be kept open, and multiple reads or writes could be performed to any of the columns in the row. Each column access was initiated by asserting and presenting a column address. For reads, after a delay (tCAC), valid data would appear on the data out pins, which were held at high-Z before the appearance of valid data. For writes, the write enable signal and write data would be presented along with the column address. Page mode DRAM was later improved with a small modification which further reduced latency. DRAMs with this improvement were called fast page mode DRAMs (FPM DRAMs). In page mode DRAM, was asserted before the column address was supplied. In FPM DRAM, the column address could be supplied while was still deasserted. The column address propagated through the column address data path, but did not output data on the data pins until was asserted. Prior to being asserted, the data out pins were held at high-Z. FPM DRAM reduced tCAC latency. Fast page mode DRAM was introduced in 1986 and was used with Intel 80486. Static column is a variant of fast page mode in which the column address