attempts to raise the abstraction level of hardware design in order to reduce the complexity of programming in HDLs, creating a sub-field called high-level synthesis. Companies such as Cadence, Synopsys and Agility Design Solutions are promoting SystemC as a way to combine high-level languages with concurrency models to allow faster design cycles for FPGAs than is possible using traditional HDLs. Approaches based on standard C or C++ (with libraries or other extensions allowing parallel programming) are found in the Catapult C tools from Mentor Graphics, and the Impulse C tools from Impulse Accelerated Technologies. A similar initiative from Intel is the use of Data Parallel C++, related to SYCL, as a high-level synthesis language. Annapolis Micro Systems, Inc.'s CoreFire Design Suite and National Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design entry and languages such as SystemVerilog, SystemVHDL, and Handel-C seek to accomplish the same goal, but are aimed at making existing hardware engineers more productive, rather than making FPGAs more accessible to existing software engineers. It is also possible to design hardware modules using MATLAB and Simulink using the MathWorks HDL Coder tool or DSP Builder for Intel FPGAs or Xilinx System Generator (XSG) from Xilinx. Examples of HDLs HDLs for analog circuit design HDLs for digital circuit design The two most widely used and well-supported HDL varieties used in industry are Verilog and VHDL. HDLs for printed circuit board design Several projects exist for defining printed circuit board connectivity using language based, textual-entry methods. See also References External links Verilog-AMS Technical Subcommittee HCT - The HDL Complexity tool, used to determine design complexity. Technical communication Logic design Programming language classification