does not need to be stored in, but rather, the address inputs may be changed with held low, and the data output will be updated accordingly a few nanoseconds later. Nibble mode is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of . The difference from normal page mode is that the address inputs are not used for the second through fourth edges; they are generated internally starting with the address supplied for the first edge. Extended data out DRAM Extended data out DRAM (EDO DRAM) was invented and patented in the 1990s by Micron Technology who then licensed technology to many other memory manufacturers. EDO RAM, sometimes referred to as Hyper Page Mode enabled DRAM, is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved performance. It is up to 30% faster than FPM DRAM, which it began to replace in 1995 when Intel introduced the 430FX chipset with EDO DRAM support. Irrespective of the performance gains, FPM and EDO SIMMs can be used interchangeably in many (but not all) applications. To be precise, EDO DRAM begins data output on the falling edge of , but does not stop the output when rises again. It holds the output valid (thus extending the data output time) until either is deasserted, or a new falling edge selects a different column address. Single-cycle EDO has the ability to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same page takes two clock cycles instead of three, once the page has been selected. EDO's performance and capabilities created an opportunity to reduce the immense performance loss associated with a lack of L2 cache in low-cost, commodity PCs. This was also good for notebooks due to difficulties with their limited form factor, and battery life limitations. Additionally, for systems with an L2 cache, the availability of EDO memory improved the average memory latency seen by applications over earlier FPM implementations. Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s. It was very low cost, yet nearly as efficient for performance as the far more costly VRAM. Burst EDO DRAM