row to open. The row is held open as long as is low. , the Column Address Strobe. The address inputs are captured on the falling edge of , and select a column from the currently open row to read or write. , Write Enable. This signal determines whether a given falling edge of is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of . , Output Enable. This is an additional signal that controls output to the data I/O pins. The data pins are driven by the DRAM chip if and are low, is high, and is low. In many applications, can be permanently connected low (output always enabled), but switching can be useful when connecting multiple memory chips in parallel. This interface provides direct control of internal timing. When is driven low, a cycle must not be attempted until the sense amplifiers have sensed the memory state, and must not be returned high until the storage cells have been refreshed. When is driven high, it must be held high long enough for precharging to complete. Although the DRAM is asynchronous, the signals are typically generated by a clocked memory controller, which limits their timing to multiples of the controller's clock cycle. RAS Only Refresh Classic asynchronous DRAM is refreshed by opening each row in turn. The refresh cycles are distributed across the entire refresh interval in such a way that all rows are refreshed within the required interval. To refresh one row of the memory array using only refresh (ROR), the following steps must occur: The row address of the row to be refreshed must be applied at the address input pins. must switch from high to low. must remain high. At the end of the required amount of time, must return high. This can be done by supplying a row address and pulsing low; it is not necessary to perform any cycles. An external counter is needed to iterate over the row addresses in turn. In some designs, the CPU handled RAM refresh, among these the Zilog Z80 is perhaps the best known example, hosting a row counter in a processor register, R, and including internal timers that would periodically poll the row at R and then increment the value in the register. Refreshes were interleaved with common instructions like memory reads. In other systems,