used. Other tools support import and export or intercommunication with components modelled at other levels of abstraction. For instance, an RTL component be converted into a SystemC model using VtoC or Verilator. And High Level Synthesis can be used to convert C models of a component into an RTL implementation. Verification In ESL design and verification, verification testing is used to prove the integrity of the design of the system or device. Numerous verification techniques may be applied; these test methods are usually modified or customized to better accommodate the system or device under test. Common ESL verification methods include, but are not limited to: Modular architecture Constrained random stimulus generation Error injection Complete simulation environments Verification is often provided by the system/device designer, but in many instances, additional independent verification is required Challenges and criticism Some criticisms of ESL design and verification have been raised. These include too much focus on C-based languages and challenges in representing parallel processes. It can also be argued that ESL design and verification is a subset of verification and validation. See also High-level synthesis High-level verification Electronic design automation Platform-based design Integrated circuit design Register-transfer level Property Specification Language Virtual prototyping SystemC SystemC AMS Systems engineering SystemVerilog Transaction-level modeling (TLM) References Further reading Electronic design automation