times its RC time constant τ; therefore 5·τ = FO4. Some examples of high-frequency CPUs with long pipeline and low stage delay: IBM Power6 has design with cycle delay of 13 FO4; clock period of Intel's Pentium 4 at 3.4 GHz is estimated as 16.3 FO4. See also Logical effort Fan-in References External links Logical Effort Revisited Revisiting the FO4 Metric // RWT, Aug 15, 2002 David Harris, Slides on Logical Effort – with a succinct example of design using FO4 inverters (p. 19). MS Hrishikesh, The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays // ACM SIGARCH Computer Architecture News. Vol. 30. No. 2. IEEE Computer Society, 2002 Electronic design