of interrupts per card, when that is useful. There is also a slight performance advantage. In software, a pin-based interrupt could race with a posted write to memory. That is, the PCI device would write data to memory and then send an interrupt to indicate the DMA write was complete. However, a PCI bridge or memory controller might buffer the write in order to not interfere with some other memory use. The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so the race is eliminated. MSI types PCI defines two optional extensions to support Message Signalled Interrupts, MSI and MSI-X. PCI Express defines its own message-based mechanism to emulate legacy PCI interrupts. MSI MSI (first defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. The device is programmed with an address to write to (generally a control register in an interrupt controller), and a 16-bit data word to identify it. The interrupt number is added to the data word to identify the interrupt. Some platforms such as Windows do not use all 32 interrupts but only use up to 16 interrupts. MSI-X MSI-X (first defined in PCI 3.0) permits a device to allocate up to 2048 interrupts. The single address used by original MSI was found to be restrictive for some architectures. In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high-speed networking applications. MSI-X allows a larger number of interrupts and gives each one a separate target address and data word. Devices with MSI-X do not necessarily support 2048 interrupts. Optional features in MSI (64-bit addressing and interrupt masking) are also mandatory with MSI-X. PCI Express legacy interrupt emulation PCI Express does not have physical interrupt pins, but emulates the 4 physical interrupt pins of PCI via dedicated PCI Express Messages such as Assert_INTA and Deassert_INTC. Being message-based (at the PCI Express layer), this mechanism provides some, but not all, of the advantages of the PCI layer MSI mechanism: the 4 virtual pins per device are no longer shared on the bus (although PCI Express controllers