the figure where the integrator, and not the flat gain, is used), the DLL is a loop of 1st order and type 1 and the PLL of 2nd order and type 2. Without the integration of the error signal, the DLL would be 0th order and type 0, and the PLL 1st order and type 1. The number of elements in the delay chain must be even, or else the duty cycle of the clock at the intermediate nodes of the chain might become irregular. If 2N +1 was the -odd- number of stages, a 50% duty-cycle would become at times N/(2N+1), at times (N+1)/(2N+1), following the jittering of the error signal around the value corresponding to perfect lock. Calling 2N the number of stages of the DLL chain, it is easy to see that the figure above would change from a DLL to a PLL, locked to the same phase and frequency, if the following modifications were made: dividing by two the number of stages making one of the stages an inverting one connecting the input of the chain of stages to its output instead of to the reference clock. The resulting chain becomes a ring oscillator with a period equal to the delay of the previous chain, and the loop locks to the same reference clock with the same level of error signal. The loop order and type are both incremented by one. It may be further remarked that, in the case where the integrator instead of the flat gain is chosen, the PLL that can be obtained is unstable. The phase shift can be specified either in absolute terms (in delay chain gate units), or as a proportion of the clock period, or both. See also Phase-locked loop (PLL) Digital Clock Manager (DCM) Clock signal References The Delay Lock Loop has been derived by J.J. Spilker, JR. and D.T. Magill, "The delay-lock discriminator--an optimum tracking device," Proc. IRE, vol.49, pp. 1403–1416, September 1961. Electronic oscillators Gate arrays Integrated circuits Digital electronics Electronic design