gate pin under consideration is grounded, and this test vector is applied to the circuit, at least one of the output bits will not agree with the corresponding output bit in the test vector. After obtaining the test vectors for grounded pins, each pin is connected in turn to a logic one and another set of test vectors is used to find faults occurring under these conditions. Each of these faults is called a single stuck-at-0 (s-a-0) or a single stuck-at-1 (s-a-1) fault, respectively. This model worked so well for transistor-transistor logic (TTL), which was the logic of choice during the 1970s and 1980s, that manufacturers advertised how well they tested their circuits by a number called "stuck-at fault coverage", which represented the percentage of all possible stuck-at faults that their testing process could find. While the same testing model works moderately well for CMOS, it is not able to detect all possible CMOS faults. This is because CMOS may experience a failure mode known as a stuck-open fault, which cannot be reliably detected with one test vector and requires that two vectors be applied sequentially. The model also fails to detect bridging faults between adjacent signal lines, occurring in pins that drive bus connections and array structures. Nevertheless, the concept of single stuck-at faults is widely used, and with some additional tests has allowed industry to ship an acceptable low number of bad circuits. The testing based on this model is aided by several things: A test developed for a single stuck-at fault often finds a large number of other stuck-at faults. A series of tests for stuck-at faults will often, purely by serendipity, find a large number of other faults, such as stuck-open faults. This is sometimes called "windfall" fault coverage. Another type of testing called IDDQ testing measures the way the power supply current of a CMOS integrated circuit changes when a small number of slowly changing test vectors are applied. Since CMOS draws a very low current when its inputs are static, any increase in that current indicates a potential problem. See also Design for test Digital electronics Electronic design automation