three bytes per instruction. The basic architecture of the 65C02 is identical to the original 6502, and can be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power system-on-chip (SoC) designs. A Verilog hardware description model is available for designing the W65C02S core into an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system. The W65C02S–14 is the production version , and is available in PDIP, PLCC and QFP packages. The maximum officially supported Ø2 (primary) clock speed is 14 MHz when operated at 5 volts, indicated by the –14 part number suffix (hobbyists have developed 65C02 homebrew systems that run faster than the official rating). The "S" designation indicates that the part has a fully static core, a feature that allows Ø2 to be slowed down or fully stopped in either the high or low state with no loss of data. Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values. General logic features 8-bit data bus 16-bit address bus (providing an address space of 64 KB) 8-bit arithmetic logic unit (ALU) 8-bit processor registers: accumulator stack pointer index registers status register 16-bit program counter 69 instructions, implemented by 212 operation codes 16 addressing modes, including zero page addressing Logic features Vector pull (VPB) output indicates when interrupt vectors are being addressed Memory lock (MLB) output indicates to other bus masters when a read-modify-write instruction is being processed WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events Electrical features Supply voltage specified at 1.71 V to 5.25 V Current consumption (core) of 0.15 and 1.5 mA per MHz at 1.89 V and 5.25 V respectively Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings Fully static circuitry allows stopping the clock to conserve