(RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller. All single-ended lines are active-low; an asserted signal or logical 1 is represented by a low voltage. The request bus operates at double data rate relative to the clock input. Two consecutive 12-bit transfers (beginning with the falling edge of CFM) make a 24-bit command packet. The data bus operates at 8x the speed of the clock; a 400 MHz clock generates 3200 MT/s. All data reads and writes operate in 16-transfer bursts lasting 2 clock cycles. Request packet formats are as follows: There are a large number of timing constraints giving minimum times that must elapse between various commands (see ); the DRAM controller sending them must ensure they are all met. Some commands contain delay fields; these delay the effect of that command by the given number of clock cycles. This permits multiple commands (to different banks) to take effect on the same clock cycle. Row activate command This operates equivalently to standard SDRAM's activate command, specifying a row address to be loaded into the bank's sense amplifier array. To save power, a chip may be configured to only activate a portion of the sense amplifier array. In this case, the SR1..0 bits specify the half or quarter of the row to activate, and following read/write commands' column addresses are required to be limited to that portion. (Refresh operations always use the full row.) Read/write commands These operate analogously to a standard SDRAM's read or write commands, specifying a column address. Data is provided to the chip a few cycles after a write command (typically 3), and is output by the chip several cycles after a read command (typically 6). Just as with other forms of SDRAM, the DRAM controller is responsible for ensuring that the data bus is not scheduled for use in both directions at the same time. Data is always transferred in 16-transfer bursts, lasting 2 clock cycles. Thus, for a ×16 device, 256 bits (32 bytes) are transferred per burst. If the chip is using a data bus less than 16 bits wide, one or more of the sub-column address bits are used to select the portion of the column to be presented on the data bus. If the data