the memory controller. The refresh counter is also programmable by the controller. Operations are: 000: NOPR Perform no refresh operation 001: REFP Refresh precharge; end the refresh operation on the selected bank. 010: REFA Refresh activate; activate the row selected by the REFH/M/L register and selected bank for refresh. 011: REFI Refresh & increment; as for REFA, but also increment the REFH/M/L register. 100: LRR0 Load refresh register low; copy RQ7–0 to the low 8 bits of the refresh counter REFL. No command delay. 101: LRR1 Load refresh register middle; copy RQ7–0 to the middle 8 bits of the refresh counter REFM. No command delay. 110: LRR2 Load refresh register high; copy RQ7–0 to the high 8 bits of the refresh counter REFH (if implemented). No command delay. 111 reserved Calibrate/powerdown command This command performs a number of miscellaneous functions, as determined by the XOPx field. Although there are 16 possibilities, only 4 are actually used. Three subcommands start and stop output driver calibration (which must be performed periodically, every 100 ms). The fourth subcommand places the chip in power-down mode. In this mode, it performs internal refresh and ignores the high-speed data lines. It must be woken up using the low-speed serial bus. Low-speed serial bus XDR DRAMs are probed and configured using a low-speed serial bus. The RST, SCK, and CMD signals are driven by the controller to every chip in parallel. The SDI and SDO lines are daisy-chained together, with the last SDO output connected to the controller, and the first SDI input tied high (logic 0). On reset, each chip drives its SDO pin low (1). When reset is released, a series of SCK pulses are sent to the chips. Each chip drives its SDO output high (0) one cycle after seeing its SDI input high (0). Further, it counts the number of cycles that elapse between releasing reset and seeing its SDI input high, and copies that count to an internal chip ID register. Commands sent by the controller over the CMD line include an address which must match the chip ID field. General structure of commands Each command either reads or writes a single 8-bit register, using an 8-bit address. This allows up to 256 registers, but only the range 1–31 is currently assigned. Normally, the CMD line is left high (logic 0) and SCK pulses have no effect. To send a command, a