sequence of 32 bits is clocked out over the CMD lines: 4 bits of 1100, a command start signal. A read/write bit. If 0, this is a read, if 1 this is a write. A single/broadcast bit. If 0, only the device with the matching ID is selected. If 1, all devices execute the command. 6 bits of serial device ID. Device IDs are automatically assigned, starting with 0, on device reset. 8 bits of register address A single bit of "0". This provides time to process read requests, and enable the SDO output in case of a read, 8 bits of data. If this is a read command, the bits provided must be 0, and the register's value is produced on the SDO pin of the selected chip. All non-selected chips connect their SDI inputs to their SDO outputs, so the controller will see the value. A single bit of "0". This ends the command and provides time to disable the SDO output. See also RDRAM XDR2 DRAM List of device bandwidths References External links Rambus XDR Product Page Rambus FlexIO CPU Inte, rface provides XDR Interface Qimonda XDR(TM) DRAM product SDRAM