this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode. During decimal mode arithmetic, the NMOS 6502 will update the (N)egative, o(V)erflow and (Z)ero flags to reflect the result of underlying binary arithmetic, that is, the flags are reflecting a result computed prior to the processor performing decimal correction. In contrast, the 65C02 sets these flags according to the result of decimal arithmetic, at the cost of an extra clock cycle per arithmetic instruction. When executing a read-modify-write (R-M-W) instruction, such as INC addr, all NMOS variants will do a double write on addr, first rewriting the current value found at addr and then writing the modified value. This behavior can result in difficult-to-resolve bugs if addr is a hardware register. This may occur if the hardware is watching for changes to the value in the register and then performs an action, in this case, it will perform two actions, one with the original value and then again with the new value. The 65C02 instead performs a double read of addr, followed by a single write. When performing indexed addressing, if indexing crosses a page boundary all NMOS variants will read from an invalid address before accessing the correct address. As with a R-M-W instruction, this behavior can cause problems when accessing hardware registers via indexing. The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary. However, this fix introduced a new bug that occurs when the base address is on an even page boundary (which means indexing will never cross into the next page). With the new bug, a dummy read is performed on the base address prior to indexing, such that LDA $1200,X will do a dummy read on prior to the value of X being added to . Again, if indexing on hardware register addresses, this bug can result in undefined behavior. If an NMOS 6502 is fetching a BRK (software interrupt) opcode at the same time a hardware interrupt occurs, the BRK will be ignored as the processor reacts to the hardware interrupt. The 65C02 correctly handles this situation by servicing the interrupt and then executing BRK. New addressing modes The 6502 has two indirect addressing modes which dereference through 16-bit addresses stored in page zero: