by an amount equal to the delay of the added clock delay buffer. A common misconception about intentional clock skew is that it is necessarily more dangerous than zero clock skew, or that it requires more precise control of delays in the clock distribution network. However it is the zero skew circuit of Figure 1 that is closer to malfunctioning - a small amount of positive clock skew for the FF2 -> FF3 pair will cause a hold violation, whereas the intentional skew circuit of Figure 2 is more tolerant of unintended delay variations in clock distribution. Optimal skew If the clock arrival times at individual registers are viewed as variables to be adjusted in order to minimize the clock period while satisfying the setup and hold inequalities for all of the paths through the circuit, then the result is a Linear Programming problem. In this linear program, zero clock skew is merely a feasible point - the solution to the linear program generally gives a clock period that is less than what is achieved by zero skew. In addition, safety margins greater than or equal to the zero skew case can be guaranteed by setting setup and hold times and jitter bound appropriately in the linear program. Due to the simple form of this linear program, an easily programmed algorithm is available for arriving at a solution. Most CAD systems for VLSI and FPGA design contain facilities for optimizing clock skews. Confusion between clock skew and clock jitter In addition to clock skew due to static differences in the clock latency from the clock source to each clocked register, no clock signal is perfectly periodic, so that the clock period or clock cycle time varies even at a single component, and this variation is known as clock jitter. At a particular point in a clock distribution network, jitter is the only contributor to the clock timing uncertainty. As an approximation, it is often useful to discuss the total clock timing uncertainty between two registers as the sum of spatial clock skew (the spatial differences in clock latency from the clock source), and clock jitter (meaning the non-periodicity of the clock at a particular point in the network). Unfortunately, spatial clock skew varies in time from one cycle to the next due to local time-dependent variations in the power supply, local temperature, and noise coupling to other signals. Thus, in