XDR DRAM (extreme data rate dynamic random-access memory) is a high-performance dynamic random-access memory interface. It is based on and succeeds RDRAM. Competing technologies include DDR2 and GDDR4. Overview XDR was designed to be effective in small, high-bandwidth consumer systems, high-performance memory applications, and high-end GPUs. It eliminates the unusually high latency problems that plagued early forms of RDRAM. Also, XDR DRAM has heavy emphasis on per-pin bandwidth, which can benefit further cost control on PCB production. This is because fewer lanes are needed for the same amount of bandwidth. Rambus owns the rights to the technology. XDR is used by Sony in the PlayStation 3 console. Technical specifications Performance Initial clock rate at 400 MHz. (ODR): Eight bits per clock cycle per lane. Each chip provides 8, 16, or 32 programmable lanes, providing up to 230.4 Gbit/s (28.8 GB/s) at 900 MHz (7.2 GHz effective). Features Bi-directional differential Rambus Signalling Levels (DRSL) This uses differential open-collector driver, voltage swing 0.2V. It is not the same as LVDS. Programmable on-chip termination Adaptive impedance matching Eight bank memory architecture Up to four bank-interleaved transactions at full bandwidth Point-to-point data interconnect Chip scale package packaging Dynamic request scheduling Early-read-after-write support for maximum efficiency Zero overhead refresh Power requirements 1.8 V Vdd Programmable ultra-low-voltage DRSL 200 mV swing Low-power PLL/DLL design Power-down self-refresh support Dynamic data width support with dynamic clock gating Per-pin I/O power-down Sub-page activation support Ease of system design Per-bit FlexPhase circuits compensate to a 2.5 ps resolution XDR Interconnect uses minimum pin count Latency 1.25/2.0/2.5/3.33 ns request packets Protocol An XDR RAM chip's high-speed signals are a differential clock input (clock from master, CFM/CFMN), a 12-bit single-ended request/command bus (RQ11..0), and a bidirectional differential data bus up to 16 bits wide (DQ15..0/DQN15..0). The request bus may be connected to several memory chips in parallel, but the data bus is point to point; only one RAM chip may be connected to it. To support different amounts of memory with a fixed-width memory controller, the chips have a programmable interface width. A 32-bit-wide DRAM controller may support 2 16-bit chips, or be connected to 4 memory chips each of which supplies 8 bits of data, or up to 16 chips configured with 2-bit interfaces. In addition, each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line