allowing it to be replaced by a variable name or calculated number. BBR bit#,offset,addr and BBS bit#,offset,addr, Branch on Bit Set/Reset. Same zero-page addressing and limitations as RMB and SMB, but branches to addr if the selected bit is clear (BBR) or set (BBS). As is the case with RMB and SMB, BBR and BBS replace a sequence of three instructions. Low-power modes In addition to the new commands above, WDC also added the STP and WAI instructions for supporting low-power modes. , STop the Processor, halted all processing until a hardware reset was issued. This could be used to put a system to "sleep" and then rapidly wake it with a reset. Normally this would require some external system to maintain main memory, and it was not widely used. t had a similar effect, entering low-power mode, but this instruction woke the processor up again on the reception of an interrupt. Previously, handling an interrupt generally involved running a loop to check if an interrupt has been received, sometimes known as "spinning", checking the type when one is received, and then jumping to the processing code. This meant the processor was running during the entire process, even when no interrupts were occurring. In contrast, in the 65C02, interrupt code could be written by having a followed immediately by a or to the handler. When the was encountered, processing stopped and the processor went into low-power mode. When the interrupt was received, it immediately processed the and handled the request. This had the added advantage of slightly improving performance. In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends one cycle to save its location. With , the processor enters the low-power state in a known location where all instructions are guaranteed to be complete, so when the interrupt arrives it cannot possibly interrupt an instruction and the processor can safely continue without spending a cycle saving state. 65SC02 The 65SC02 is a variant of the WDC 65C02 without bit instructions. Notable uses of the 65C02 Home computers Apple IIc portable by Apple Computer (NCR 1.023 MHz) Enhanced Apple IIe by Apple Computer (1.023 MHz) BBC Master home/educational computer, by Acorn Computers Ltd (2 MHz 65SC12 plus optional 4 MHz 65C102 second processor) Replica 1 by Briel Computers, a