register. Harmful skew There are two types of violation that can be caused by clock skew. One problem is caused when the clock reaches the first register and the clock signal towards the second register travels slower than output of the first register into the second register - the output of the first register reaches the second register input faster and therefore is clocked replacing the initial data on the second register, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew and negative skew cannot negatively impact setup and hold timing constraints respectively (see inequalities below). Beneficial skew Where a signal broadly clocks a circuit, the signals/state-transitions it initiates must be stabilized before it signals another set of state transitions -- and that limits the clock's upper frequency. Skew thus decreases the clock frequency at which the circuit will operate correctly. For each source register and destination register connected by a path, the following setup and hold inequalities must be obeyed: where T is the clock period, reg is the source register's clock to Q delay, is the path with the longest delay from source to destination, J is an upper bound on jitter, S is the setup time of the destination register represents the clock skew from the source to the destination registers, is the path with the shortest delay from source to destination, H is the hold time of the destination register, is the clock skew to the destination register, and is the clock skew to the source register. Positive clock skews are good for fixing setup violations, but can cause hold violations. Negative clock skew can guard against a hold violation, but can cause a setup violation. In the above inequalities, a single parameter, J, is used to