bus is 8 bits wide, SC3 is used to identify which half of the read data to access; if the data bus is 4 bits wide, SC3 and SC2 are used, etc. Unlike conventional SDRAM, there is no provision for choosing the order in which the data is supplied within a burst. Thus, it is not possible to perform critical-word-first reads. Masked write command The masked write command is similar to a normal write, but no command delay is permitted and a mask byte is supplied. This permits controlling which 8-bit fields are written. This is not a bitmap indicating which bytes are to be written; it would not be large enough for the 32 bytes in a write burst. Rather, it is a bit pattern which the DRAM controller fills unwritten bytes with. The DRAM controller is responsible for finding a pattern which does not appear in the other bytes that are to be written. Because there are 256 possible patterns and only 32 bytes in the burst, it is straightforward to find one. Even when multiple devices are connected in parallel, a mask byte can always be found when the bus is at most 128 bits wide. (This would produce 256 bytes per burst, but a masked write command is only used if at least one of them is not to be written.) Each byte is the 8 consecutive bits transferred across one data line during a particular clock cycle. M0 is matched to the first data bit transferred during a clock cycle, and M7 is matched to the last bit. This convention also interferes with performing critical-word-first reads; any word must include bits from at least the first 8 bits transferred. Precharge/refresh command This command is similar to a combination of a conventional SDRAM's precharge and refresh commands. The POPx and BPx bits specify a precharge operation, while the ROPx, DELRx, and BRx bits specify a refresh operation. Each may be separately enabled. If enabled, each may have a different command delay and must be addressed to a different bank. Precharge commands may only be sent to one bank at a time; unlike a conventional SDRAM, there is no "precharge all banks" command. Refresh commands are also different from a conventional SDRAM. There is no "refresh all banks" command, and the refresh operation is divided into separate activate and precharge operations so the timing is determined by