account for jitter. This parameter must be an upper bound for the difference in jitter over all source register/destination register pairs. However, if the structure of the clock distribution network is known, different source register/destination register pairs may have different jitter parameters, and a different jitter value may be used for the hold constraint in contrast to the value for the setup constraint. For example, if the source register and destination register receive their clock signals from a common nearby clock buffer, the jitter bound for that hold constraint can be very small, since any variation in that clock signal will affect the two registers equally. For the same example, the jitter bound for the setup constraint must be larger than for the hold constraint, because jitter can vary from clock tick to clock tick. If the source register receives its clock signal from a leaf buffer of the clock distribution network that is far removed from the leaf buffer feeding the destination register, then the jitter bound will have to be larger to account for the different clock paths to the two registers, which may have different noise sources coupling into them. Figures 1 and 2 illustrate a situation where intentional clock skew can benefit a synchronous circuit. In the zero-skew circuit of Figure 1, a long path goes from flip-flop FF1 to flip-flop FF2, and a short path, such as a shift-register path, from FF2 to FF3. The FF2 -> FF3 path is dangerously close to having a hold violation: If even a small amount of extra clock delay occurs at FF3, this could destroy the data at the D input of FF3 before the clock arrives to clock it through to FF3's Q output. This could happen even if FF2 and FF3 were physically close to each other, if their clock inputs happened to come from different leaf buffers of a clock distribution network. Figure 2 shows how the problem can be fixed with intentional clock skew. A small amount of extra delay is interposed before FF2's clock input, which then safely positions the FF2 -> FF3 path away from its hold violation. As an added benefit, this same extra clock delay relaxes the setup constraint for the FF1 -> FF2 path. The FF1 -> FF2 path can operate correctly at a clock period that is less than what is required for the zero clock skew case,