in the accumulator unchanged, so subsequent code can make additional tests against the original value, avoiding having to re-load the value from memory. In addition to the enhancements of the BIT instruction, WDC added two instructions designed to conveniently manipulate bit fields: TSB addr and TRB addr, Test and Set Bits and Test and Reset Bits. A mask in the accumulator (.A) is logically ANDed with memory at addr, which location may be zero page or absolute. The Z flag in the status register is conditioned according to the result of the logical AND—no other status register flags are affected. Furthermore, bits in addr are set (TSB) or cleared (TRB) according to the mask in .A. Succinctly, TSB performs a logical OR after the logical AND and stores the result of the logical OR at addr, whereas TRB stores the results of the logical AND at addr. In both cases, the Z flag in the status register indicates the result of .A AND addr before the content of addr is changed. TRB and TSB thus replace a sequence of instructions, essentially combining the BIT instruction with additional steps to save the computational changes, but in a way that reports the status of the affected value before it is changed. Rockwell's changes added more bit manipulation instructions for directly setting and testing any bit, and combining the test, clear and branch into a single opcode. The new instructions were available from the start in Rockwell's R65C00 family, but was not part of the original 65C02 specification and not found in versions made by WDC or its other licensees. These were later copied back into the baseline design, and were available in later WDC versions. Rockwell-specific instructions are: SMBbit# zp/RMBbit# zp. Set or Reset (clear) bit number bit# in zero page byte zp. RMB and SMB are used to clear (RMB) or set (SMB) individual bits in a bit field, each replacing a sequence of three instructions. As RMB and SMB are zero page addressing only, these instructions are limited in usefulness and are primarily of value in systems in which device registers are present in zero page. The bit# component of the instruction is often written as part of the mnemonic, such as SMB1 $12 which sets bit 1 in zero-page address $12. Some assemblers treat bit# as part of the instruction's operand, e.g., SMB 1,$12, which has the advantage of