along with Tohoku University. In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device at time, based on FinFET technology. In 2010, researchers at the Tyndall National Institute in Cork, Ireland announced a junctionless transistor. A control gate wrapped around a silicon nanowire can control the passage of electrons without the use of junctions or doping. They claim these may be produced at 10-nm scale using existing fabrication techniques. In 2011, researchers at the University of Pittsburgh announced the development of a single-electron transistor, 1.5 nm in diameter, made out of oxide-based materials. Three "wires" converge on a central "island" that can house one or two electrons. Electrons tunnel from one wire to another through the island. Conditions on the third wire result in distinct conductive properties including the ability of the transistor to act as a solid state memory. Nanowire transistors could spur the creation of microscopic computers. In 2012, a research team at the University of New South Wales announced the development of the first working transistor consisting of a single atom placed precisely in a silicon crystal (not just picked from a large sample of random transistors). Moore's law predicted this milestone to be reached for ICs in the lab by 2020. In 2015, IBM demonstrated 7 nm node chips with silicon-germanium transistors produced using EUVL. The company believes this transistor density would be four times that of current 14 nm chips. Samsung and TSMC plan to manufacture 3nm GAAFET nodes by 20212022. Note that node names, such as 3nm, have no relation to the physical size of device elements (transistors). A Toshiba research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing three-dimensional integrated circuit (3D IC) packages in 2001. In April 2007, Toshiba introduced an eight-layer 3D IC, the 16GB THGAM embedded NAND flash memory chip which was manufactured with eight stacked 2GB NAND flash chips. In September 2007, Hynix introduced 24-layer 3D IC, a 16GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process. V-NAND, also known as 3D NAND, allows flash memory cells to be stacked vertically using charge trap flash technology originally presented by John Szedon in 1967, significantly increasing the