both go to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC's output matches the input signal and number is read from the counter. Delta converters have very wide ranges and high resolution, but the conversion time is dependent on the input signal behavior, though it will always have a guaranteed worst-case. Delta converters are often very good choices to read real-world signals as most signals from physical systems do not change abruptly. Some converters combine the delta and successive approximation approaches; this works especially well when high frequency components of the input signal are known to be small in magnitude. Pipelined A pipelined ADC (also called subranging quantizer) uses two or more conversion steps. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a DAC. This difference is then converted more precisely, and the results are combined in the last step. This can be considered a refinement of the successive-approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and can be implemented efficiently. Sigma-delta A sigma-delta ADC (also known as a delta-sigma ADC) is based on a feedback loop with an analog filter and low resolution (often 1 bit), but high speed ADC and DAC to approximate the incoming signal. The filter (usually a 2nd order low pass filter) in the loop performs noise shaping: the quantization noise originating from the DAC is no longer evenly distributed over the frequencies, but higher for the high frequencies and reduced for the low frequencies. A digital filter (decimation filter) than removes much of the higher frequencies (especially much of the quantization noise) and converts the data stream from high sampling rate and low resolution to low speed and high resolution. Time-interleaved A time-interleaved ADC uses M parallel ADCs where each ADC samples data every M:th cycle of the effective sample clock. The result is that the sample rate is increased M times compared to what each individual ADC can manage. In practice, the individual differences between the M ADCs degrade the overall performance reducing the spurious-free dynamic range (SFDR). However,