by a memory controller on the memory bus based on a set timing rather than a clock, and was separate from the system bus. Synchronous DRAM, however, has a CAS latency that is dependent upon the clock rate. Accordingly, the CAS latency of an SDRAM memory module is specified in clock ticks instead of absolute time. Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, pipeline stalls can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time. Because modern DRAM modules' CAS latencies are specified in clock ticks instead of time, when comparing latencies at different clock speeds, latencies must be translated into absolute times to make a fair comparison; a higher numerical CAS latency may still be less time if the clock is faster. Likewise, a memory module which is underclocked could have its CAS latency cycle count reduced to preserve the same CAS latency time. Double data rate (DDR) RAM performs two transfers per clock cycle, and it is usually described by this transfer rate. Because the CAS latency is specified in clock cycles, and not transfers (which occur on both the rising and falling edges of the clock), it is important to ensure it is the clock rate (half of the transfer rate) which is being used to compute CAS latency times. Another complicating factor is the use of burst transfers. A modern microprocessor might have a cache line size of 64 bytes, requiring eight transfers from a 64-bit-wide (eight bytes) memory to fill. The CAS latency can only accurately measure the time to transfer the first word of memory; the time to transfer