dies Four dies implement the level 1 (L1) instruction and data caches, which require two dies each. Both caches have a capacity of 128 KB. The latency for both caches is three cycles, and the caches are four-way set associative. The data cache is protected by error correcting code (ECC) and parity. It uses a 128-byte line size. Each CACHE die implements 64 KB of the cache and a portion of the cache tags. The cache die contains 4.3 million transistors, has dimensions of 14.0 mm by 10.11 mm for a die area of 142 mm2. It has 1,854 solder bumps, of which 446 are signals and 1408 are power. Physical The SPARC64 consisted of 21.9 million transistors. It was fabricated by Fujitsu in their CS-55 process, a 0.40 μm, four-layer metal complementary metal–oxide–semiconductor (CMOS) process. The seven dies are packaged in a rectangular ceramic multi-chip module (MCM), connected to the underside of the MCM with solder bumps. The MCM has 565 pins, of which 286 are signal pins and 218 are power pins, organized as a pin grid array (PGA). The MCM has wide buses which connect the seven dies. SPARC64 II The SPARC64 II (SPARC64+) was a further development of the SPARC64. It is a second-generation SPARC64 microprocessor. It operated at 141 and 161 MHz. It was used by Fujitsu in their HALstation Model 375 (141 MHz) and Model 385 (161 MHz) workstations, which were introduced in November 1996 and December 1996, respectively. The SPARC64 II was succeeded by the SPARC64 III in 1998. The SPARC64 II has higher performance due to higher clock frequencies enabled by the new process and circuit tweaks; and a higher instructions per cycle (IPC) count due to the following microarchitecture improvements: The capacity of the level 0 (L0) instruction cache was doubled to 8 KB. The number of physical registers was increased to 128 from 116 and the number of register files to five from four. The number of branch history table entries was doubled to 2,048. It was fabricated by Fujitsu in their CS-60 process, a 0.35 μm, five-layer metal CMOS process. The new process reduced the area of the dies, with the CPU die measuring 202 mm2, the MMU die 103 mm2, and the CACHE die 84 mm2. SPARC64 GP The SPARC64 GP is a series of related microprocessors developed by HAL and Fujitsu used in the Fujitsu GP7000F and