can be directly accessed and used as secondary accumulators, labeled A through J. The rest of the scratchpad is accessed through the ISAR, a form of indirect addressing. The 3851/3852/3853 contain the program counter, , along with a secondary program counter, . was referred to as a stack pointer but was not actually used for this, it was used only to store the return addresses from subroutines and lacked any push or pop instructions. If a larger stack is required, this has to be implemented in software. These chips also had a 16-bit Data Counter, , and its associated Data Counter Buffer, . These were used as indexing registers for indirect addressing, although only could be accessed directly and the value in had to be swapped with using a separate instruction. The instruction set included 70 opcodes encoded in 8-bits. As was typical of the era, many instructions had a variety of addressing modes with some of the modes encoded in the instruction opcode. For instance, the Load Register (LR) instruction came in 14 different versions depending on the origin and destination of the data. The version starting with was followed by two zero bits and then another two bits indicating locations in the scratchpad in locations 12 through 15, so this used opcodes through . was another version of LR, loading the value pointed to by the ISAR. The F8 had a total of eight addressing modes. The machine instructions can be grouped into six categories: accumulator instructions, branch instructions, memory reference instructions, address register instructions, scratchpad register instruction, miscellaneous instructions (interrupt, input, output, indirect scratchpad register, load, and store). The F8 ran at , yielding a cycle time. In the F8 the control bus regulates the use of the data bus through the use of timing signals and state controls. The phi clock divides the machine cycle into discrete phases depending on the instruction being executed. The five state control lines are a function of the instruction being executed. The control bus states regulate the control of information in the computer. FAIR-BUG Fairchild provided development and evaluation kits for the F8, these kits included a 3851A PSU (Program Storage Unit) which contained a monitor in mask ROM, vectored to start at address 0x8080. At power-on, the ROM was entered. The ROM monitor was referred to in Fairchild literature as FAIR-BUG. The FAIR-BUG monitor is a constellation of routines