the functions, like adding a small amount of RAM to the CPU core, while moving others out of the CPU. The best example of this is the minimal system consisting of the 3850 CPU and 3851 PSU. In this case, there is no need for an address bus at all, the RAM is contained in the 3850 and the program ROM in the 3851. It is the PSU that is responsible for keeping track of the program counter, fetching instructions from the internal ROM and feeding them to the 3850 for processing over a dedicated 5-pin instruction bus along with any associated data over the separate 8-bit data bus. This freed up 11 pins that would otherwise be used for additional address lines, which, along with other simplifications and splitting of duty, allowed the CPU to have two complete I/O busses. The 3851 added another two I/O ports, so that a minimal system had four ports in total. With only 1 KB of ROM and 64 bytes of RAM, only small programs can be managed, but for many systems, like cash registers, gasoline pumps and similar roles, this is more than enough. When a system does have larger requirements, the 3852 or 3853 can be used. These interface with the PSU and contain additional logic for handling their associated memory; for instance, the 3852 had a complete address bus able to access 64 KB of RAM and the circuitry needed to refresh the data. The PSU is still required in these systems, and the program counter and other pointers are maintained separately in all of these chips by reading the same control lines. The main difference between the 3852 and 3853 was that the former included the dynamic RAM refresh circuitry and a 3-pin link to the 3854 DMA controller, while the 3853 removed these and added a new interrupt handler and timer. The 3854 DMA controller was linked directly to the 3852 RAM controller and did not use the 5-pin control bus found on the other members of the family. It maintained its own address register and a separate byte count, which together indicated the block of memory to be read or written. Instruction set architecture Internally, the CPU contained an 8-bit accumulator, a 5-bit processor status register, a 6-bit "Indirect Scratchpad Address Register", or ISAR, and 64 bytes of "scratchpad" RAM. The first twelve locations within the RAM