PrimePower servers. The first SPARC64 GP was a further development of the SPARC64 II. It was a third-generation SPARC64 microprocessor and was known as the SPARC64 III before it was introduced. The SPARC64 GP operated at clock frequencies of 225, 250 and 275 MHz . It was the first microprocessor from HAL to support multiprocessing. The main competitors were the HP PA-8500, IBM POWER3 and Sun UltraSPARC II. The SPARC64 GP was taped out in July 1997. It was announced on 11 April 1998, with 225 and 250 MHz versions were introduced in December 1998. A 275 MHz version was introduced in March 1999. It was a single-die implementation of the SPARC64 II that integrated, with modifications, the CPU die and two of the four CACHE dies. Numerous modifications and improvements were made to the microarchitecture, such as the replacement of the MMU and a new system interface using the Ultra Port Architecture. It had improved branch prediction, an extra pipeline stage to improve clock frequencies and a second FPU which could execute add and subtract instructions. A FPU of less functionality was added instead of a duplicate of the first to save die area; the second FPU is half the size of the first. It has a three-cycle latency for all instructions. The complex SPARC64 II memory management unit (MMU) was replaced with a simpler one that is compatible with the Solaris operating system. Previously, SPARC64 systems ran SPARC64/OS, a derivative of Solaris developed by HAL that supported the SPARC64. The L1 caches were halved in capacity to 64 KB from 128 KB to reduce die area (the reason why only two of the four CACHE dies were integrated from the SPARC64 II). The associated performance loss was mitigated by the provision of a large external L2 cache with a capacity of 1 to 16 MB. The L2 cache is accessed with a dedicated 128-bit data bus that operates at the same or half clock frequency of the microprocessor. The L2 cache is inclusive, that is it is a super-set of the L1 caches. Both L1 and L2 cache have their data protected by ECC and their tags by parity. The SPARC64 II's proprietary system interface was replaced by one compatible with the Ultra Port Architecture. This enabled the SPARC64 III to use chipsets from Sun Microelectronics. The system bus operates at half, a third, quarter or fifth the