National Semiconductor's INS8060, or SC/MP (pronounced scamp) for Simple Cost-effective Micro Processor, is an early 8-bit microprocessor which became available in April 1976. A unique feature of the SC/MP is a daisy-chained control pin that allowed up to three SC/MP's share a single main memory to produce a multiprocessor system. To lower cost, the system used a bit-serial arithmetic logic unit (ALU) and was thus significantly slower than contemporary designs like the Intel 8080 or MOS 6502 which had parallel ALUs. Another oddity was that the program counter could only access the lower 12-bits of the 16-bit address, and the upper 4-bits had to be set using special instructions. The result was that instructions accessed main memory as sixteen 4 kB "pages" and reaching memory outside those pages required multiple instructions. The combination of slow speed and paged memory limited its attractiveness, especially in the markets that might need a multiprocessing system. It saw very little use in the market. Design Basic features Like most 8-bit microprocessors of the era, the SC/MP is based around a 16-bit address and an 8-bit data bus. To lower pin count, the external address bus contains only 12 pins, sharing 4 pins from the data bus to create a complete 16-bit address. Internally, the program counter is twelve bits wide, and there are separate instructions to set the upper four bits. This provides a memory map of sixteen four-kilobyte pages, and program code could not refer to code or data outside its own page. Internally it provided five registers plus the program counter. Subroutine and Interrupt handling were implemented by Pointer Register 3 (P3) although this could also be used as a general purpose 16 bit Index register. Bus control A unique feature of the SC/MP was a shared daisy-chained control line that allowed multiple SC/MP, or more commonly a single SC/MP and related direct memory access controllers, to share access to a single main memory. When any one of the chips on the bus desired access to memory, it would set the ENOUT pin high, thereby signalling the other chip's ENIN pins that they had to release the bus. With other processors, this would normally require external logic implemented by the board designers to pause the CPU to the same end, often with some complexity due to the internal instruction timing that was not visible to the external circuits. In the SC/MP this